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What’s targeted for CADSTAR 2019.0 and BML 13.1(All plans are subject to change)
Jeroen Leinders
CADSTAR Distribution Manager
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2019
CADSTAR release schedule
*The release schedule is as usual a subject of change if circumstances require!
2020 2021
Jun Sep
Beta Release
2021
Version 2021.0.0.1
Media Release (available on demand)
2021
Apr
Version 2021.0.0.0
Web Release
Customer requested
defects …
2021
...and more
*All plans are subject to change
Jul Sep
Beta Release
2019
Version 2019.0.0.1
Media Release (available on demand)
2019
Apr
Version 2019.0.0.0
Web Release
Customer requested
defects …
2019
...and more
Jun Sep
Beta Release
2020
Version 2020.0.0.1
Media Release (available on demand)
2020
Apr
Version 2020.0.0.0
Web Release
Customer requested
defects …
2020
...and more
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What’s targeted for CADSTAR 2019.0
High Resolution Monitor Support
– CADSTAR's user interface now scales smoothly and proportionally with the high resolution monitors
increasingly found in modern PC systems
– Support display scaling from 100% to 250% (92 – 230 dpi)
– CADSTAR will scale its user interface to suit
Monitor Resolution Recommended Scaling
SXGA 1280 x 1024 100 - 125%
WXGA (FHD) 1920 x 1080 100 - 125%
UHD (4K) 3840 x 2160 200 - 250%
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What’s targeted for CADSTAR 2019.0
Improvement in clarity when moving from a standard monitor to a 4K monitor
– Using CADSTAR on a high resolution display gives a whole new feel to PCB design with its smooth
display, large and clear fonts and crisp icons
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What’s targeted for CADSTAR 2019.0
Write pin identifiers in RIF even without part information.
Transferring a design to both routing and high speed tools will include the pin identifiers from the footprint
where an unallocated part is in use, instead of a number.
It will be straightforward to identify these pins on multi-pin devices like BGAs.
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What’s targeted for CADSTAR 2019.0
Retain Swapped Pins
Gate Swaps Pin Swaps
It is now possible to prevent losing swapped pin information
when replacing a part
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What’s targeted for CADSTAR 2019.0
Support for Complex Vias calculation
– When the Enable enhanced via extraction checkbox is ticked, all vias in Constraint Manager will be output
to CTF as complex vias, even if they are immediately adjacent to a component pad or are connected by
transmission lines shorter than the transmission line cut-off length to other vias or component pins.
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What’s targeted for CADSTAR 2019.0
Complex Vias Support continued…
– The representation in Scenario Editor as
it will be:
Micro-via >core via >
micro via stacked on
same x,y position
extracted as complex vias
Micro-via >core via
stacked on same x,y
position extracted as
complex vias
Only display this
transmission line if it’s
longer than the
transmission line cut-off
length
Offset via extracted as
complex via even if the
connecting track is shorter
than the transmission line
cut-off length
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What’s targeted for CADSTAR 2019.0
End-router performance
improvements
– To improve performance of the
trunk end-router to reduce
completion time and
responsiveness
• In complex cases, it is
anticipated that this will deliver
a 13-16% reduction in time. For
example, when the end-routing
process is applied to trunks with
32 connections (see right)
• In simpler cases, the
performance will be similar as in
the current implementation in
CADSTAR 2018 and earlier
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What’s targeted for CADSTAR 2019.0
PIA
– Arbitrary DC Sources
• Select a power and a ground pin from different components
• Make this combination a “Virtual DC Source”
• Run the DC Analysis with this source
– allows the user to examine the supply circuitry in more detail, i.e. from source locations where no single component can be used
– Result reload on design load
• Automatically populate PI and DC result tables on design load
– Re-loaded results are graphically indicated as such
– continue work after interruption
– Avoid the need to re-compute
– Performance improvements on design load
• Large design data are loaded significantly faster
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What’s targeted for CADSTAR 2019.0
Simulation Library Manager
– Improved IXF Import / Export
• Comprehensive repository content is now contained in the ixf-files
• Compressed file format (“.ixf” “.ixfz”)
– Improved SPICE Import for pole-residue models (e.g. used by IdEM)
• SPICE models containing higher order G-elements are now supported
– Ideal GND node is no longer added to the model interface
• Improved model compatibility and consistency, e.g. with IdEM models
– Performance improvements
• Significant speed-ups on buffer model and package data handling
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What’s targeted for CADSTAR 2019.0
Analysis Result Viewer
– Support of SI result data in SI Verify format (.vgf)
(.vgf-files created from SISS)
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13
What’s targeted for BML 13.1
Copper Trimming
– Where copper pads, or areas overlap the edge of the board the copper is automatically trimmed off
BML 12.1 (Old) BML 13.1 (New)
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14
What’s targeted for BML 13.1
Step Output
– The step output will now unite pads to the
associated routing
• Previously the route and pads were
separate geometries
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15
What’s targeted for BML 13.1
Full UNC (Universal Naming Convention) path support
– It is now possible to place designs, and libraries on a network
location without mapping the location to a drive letter
• A standard for identifying servers and other resources in a
network
• A UNC path uses double slashes or backslashes to precede
the name of the computer
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16
What’s targeted for BML 13.1
Other enhancements
– Testlands placed on the bottom electrical layer (Min) are now shown in BML
– Resist and assembly layers treated as separate layers
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