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Dr. Ahmed H. Madian-VLSI 1
Very Large Scale Integration (VLSI)
Dr. Ahmed H. Madian [email protected]
Lecture 4
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Dr. Ahmed H. Madian-VLSI 2
Contents
Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort
Delay minimization techniques Transistor sizing Wiring sizing Distributed drivers Large driver
Wiring techniques
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Dr. Ahmed H. Madian-VLSI 3
Circuit characterization & performance
Resistance estimation
Capacitance estimation
Inductance estimation
Delay estimation Simple RC model
Penfield-Rubenstein Model
Delay minimization techniques Transistor sizing
Distributed drivers
Driving large loads
Wiring techniques
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Delay Estimation
How to estimate the delay for your layout?
1- use a simulator
2- Solve the differential equation to get the exact delay
3- model your circuit using one of the defined delay models like RC
Dr. Ahmed H. Madian-VLSI 4
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Dr. Ahmed H. Madian-VLSI 5
Signal Delay Time
Signal delay time is composed as follows Gate delay time
Interconnection delay time
due to minimization the delay times decreases
the output impedance of buffers increases, thus the importance of interconnection delays increases
So, signal delay time becomes less dependent on gate delay but more dependent on interconnection delay time
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4: DC and Transient Response 6
Elmore Delay
ON transistors look like resistors
Pull-up or pull-down network modeled as RC ladder
Elmore delay of RC ladder
R1
R2
R3
RN
C1
C2
C3
CN
nodes
1 1 1 2 2 1 2... ...
pd i to source i
i
N N
t R C
R C R R C R R R C
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Dr. Ahmed H. Madian-VLSI 7
Routing Delay estimation (cont.)
W
W
Ru
Cu Cu Cu CuCu Cu Cu
Ru Ru Ru Ru Ru Ru
Elmore Delay:
Rtotal = n RU
Ctotal = n CU
total = n2RU CU
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Dr. Ahmed H. Madian-VLSI 8
Delay Estimation
For MOSFET transistor,
N+ N+
G
D S
L
velocity
Ltransit
Velocity = µ.
Where µ = mobility and = electric filed = VDS/L
DDDStransit
V
L
L
V
L
2
For lower delay,
• VDD may be increased but we have limit of break down
• L may be decreased but there’s a problem with technology and
Resistance
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Dr. Ahmed H. Madian-VLSI 9
Delay estimation (cont.)
Equivalent circuit used for MOSFET
Ideal Switch + Capacitance and ON Resistance
Unit NMOS has resistance R, Capacitance C
Unit PMOS has resistance 2R, Capacitance C
Capacitance proportional to width
Resistance is inversely proportional to width
Define a model for delay based on the unit delay
Treat every MOSFET as resistance.
Lump intermediate node capacitance with load capacitance.
u = RS * CGate of min size transistor
G
R
Vin
Cg
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Dr. Ahmed H. Madian-VLSI 10
Simple RC model
VDD
Vin
VDD
2Cg2Cg
Vin
RP
Rn
RP
Rn
•Assume all pull –up /pull-down resistors are
summed as Rpu/Rpd and all capacitance are
summed in the output capacitance
RP = 2.5Rn
u = Rn Cg
inv1 = 2 RP Cg
inv1 = 5 Rn Cg
inv2 = 2 Rn Cg
Inverter pair delay = inv1+ inv2 = 7 Rn Cg
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Dr. Ahmed H. Madian-VLSI 11
Elmore Delay Model
Calculate the delays in generalized RC trees.
For a group of transistors in series (as in
NAND gate),
Where Ri is the summed resistance from
point i to power or ground and Ci is the
capacitance at point i.
Ex.: for 4 input NAND gate the fall time
will be,
a b c d
VDD
a
b
c
d
out
Cout
Cab
Cbc
Ccd
ii
id CRt
outNNNNabNNNbcNNcdNdf xCRRRRxCRRRxCRRxCRt 4321321211 )(
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Delay Components
Delay has two parts
Parasitic delay 6 or 7 RC
Independent of load
Effort delay 4h RC
Proportional to load capacitance
Dr. Ahmed H. Madian-VLSI 12
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Logical Effort
Chip designers face a bewildering array of choices
What is the best circuit topology for a function?
How many stages of logic give least delay?
How wide should the transistors be?
Logical effort is a method to make these decisions
Uses a simple model of delay
Allows back-of-the-envelope calculations
Helps make rapid comparisons between alternatives
Emphasizes remarkable symmetries
Dr. Ahmed H. Madian-VLSI 13
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Delay Plots
d = f + p
= gh + p
Electrical Effort:h = C
out / C
in
Norm
aliz
ed D
ela
y: d
Inverter
2-input
NAND
g = 1
p = 1
d = h + 1
g = 4/3
p = 2d = (4/3)h + 2
Effort Delay: f
Parasitic Delay: p
0 1 2 3 4 5
0
1
2
3
4
5
6
Dr. Ahmed H. Madian-VLSI 14
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Computing Logical Effort
DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.
Measure from delay vs. fanout plots
Or estimate by counting transistor widths
A YA
B
YA
BY
1
2
1 1
2 2
2
2
4
4
Cin = 3
g = 3/3
Cin = 4
g = 4/3
Cin = 5
g = 5/3
Dr. Ahmed H. Madian-VLSI 15
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Example: Ring Oscillator
Estimate the frequency of an N-stage ring oscillator
Logical Effort: g =
Electrical Effort: h =
Parasitic Delay: p =
Stage Delay: d =
Frequency: fosc =
Dr. Ahmed H. Madian-VLSI 16
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Example: Ring Oscillator Estimate the frequency of an N-stage ring oscillator
Logical Effort: g = 1
Electrical Effort: h = 1
Parasitic Delay: p = 1
Stage Delay: d = 2
Frequency: fosc = 1/(2*N*d) = 1/4N
31 stage ring oscillator in
0.6 m process has
frequency of ~ 200 MHz
Dr. Ahmed H. Madian-VLSI 17
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Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter
Logical Effort: g =
Electrical Effort: h =
Parasitic Delay: p =
Stage Delay: d =
d
Dr. Ahmed H. Madian-VLSI 18
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Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter
Logical Effort: g = 1
Electrical Effort: h = 4
Parasitic Delay: p = 1
Stage Delay: d = 5
d
The FO4 delay is about
200 ps in 0.6 m process
60 ps in a 180 nm process
f/3 ns in an f m process
Dr. Ahmed H. Madian-VLSI 19
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Multistage Logic Networks
Logical effort generalizes to multistage networks
Path Logical Effort
Path Electrical Effort
Path Effort
iG gout-path
in-path
CH
C
i i iF f g h
10x
y z20
g1 = 1h
1 = x/10
g2 = 5/3h
2 = y/x
g3 = 4/3h
3 = z/y
g4 = 1h
4 = 20/z
Dr. Ahmed H. Madian-VLSI 20
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Multistage Logic Networks
Logical effort generalizes to multistage networks
Path Logical Effort
Path Electrical Effort
Path Effort
Can we write F = GH?
iG g
out path
in path
CH
C
i i iF f g h
Dr. Ahmed H. Madian-VLSI 21
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Paths that Branch
No! Consider paths that branch:
G =
H =
GH =
h1 =
h2 =
F = GH?
5
15
1590
90
Dr. Ahmed H. Madian-VLSI 22
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Paths that Branch
No! Consider paths that branch:
G = 1
H = 90 / 5 = 18
GH = 18
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH
5
15
1590
90
Dr. Ahmed H. Madian-VLSI 23
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Designing Fast Circuits
Delay is smallest when each stage bears same effort
Thus minimum delay of N stage path is
This is a key result of logical effort
Find fastest possible delay
Doesn’t require calculating gate sizes
i FD d D P
1ˆ N
i if g h F
1ND NF P
Dr. Ahmed H. Madian-VLSI 24
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Gate Sizes
How wide should the gates be for least delay?
Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives.
Check work by verifying input cap spec is met.
ˆ
ˆ
out
in
i
i
C
C
i out
in
f gh g
g CC
f
Dr. Ahmed H. Madian-VLSI 25
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Example: 3-stage path
Select gate sizes x and y for least delay from A to B
8x
x
x
y
y
45
45
A
B
Dr. Ahmed H. Madian-VLSI 26
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Example: 3-stage path
Logical Effort G =
Electrical Effort H =
Branching Effort B =
Path Effort F =
Best Stage Effort
Parasitic Delay P =
Delay D =
8x
x
x
y
y
45
45
A
B
f̂
Dr. Ahmed H. Madian-VLSI 27
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Example: 3-stage path
Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27
Electrical Effort H = 45/8
Branching Effort B = 3 * 2 = 6
Path Effort F = GBH = 125
Best Stage Effort
Parasitic Delay P = 2 + 3 + 2 = 7
Delay D = 3*5 + 7 = 22 = 4.4 FO4
8x
x
x
y
y
45
45
A
B
3ˆ 5f F
Dr. Ahmed H. Madian-VLSI 28
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Example: 3-stage path
Work backward for sizes
y =
x =
8x
x
x
y
y
45
45
A
B
Dr. Ahmed H. Madian-VLSI 29
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Example: 3-stage path
Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10
P: 4
N: 4
45
45
A
BP: 4
N: 6P: 12
N: 3
Dr. Ahmed H. Madian-VLSI 30
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Best Number of Stages
How many stages should a path use?
Minimizing number of stages is not always fastest
Example: drive 64-bit datapath with unit inverter
D =
1 1 1 1
64 64 64 64
Initial Driver
Datapath Load
N:
f:
D:
1 2 3 4
Dr. Ahmed H. Madian-VLSI 31
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Best Number of Stages
How many stages should a path use?
Minimizing number of stages is not always fastest
Example: drive 64-bit datapath with unit inverter
D = NF1/N + P
= N(64)1/N + N
1 1 1 1
8 4
16 8
2.8
23
64 64 64 64
Initial Driver
Datapath Load
N:
f:
D:
1
64
65
2
8
18
3
4
15
4
2.8
15.3
Fastest
Dr. Ahmed H. Madian-VLSI 32
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Example: 2-input NAND
Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.
h copies
2
2
22
B
A
x
Y
Dr. Ahmed H. Madian-VLSI 33
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Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
h copies
6C
2C2
2
22
4hC
B
A
x
Y
Dr. Ahmed H. Madian-VLSI 34
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Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
h copies
6C
2C2
2
22
4hC
B
A
x
Y
R
(6+4h)CY
pdrt
Dr. Ahmed H. Madian-VLSI 35
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Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
h copies
6C
2C2
2
22
4hC
B
A
x
Y
R
(6+4h)CY 6 4pdrt h RC
Dr. Ahmed H. Madian-VLSI 36
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Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
A
x
Y
Dr. Ahmed H. Madian-VLSI 37
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Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
A
x
Y
pdft (6+4h)C2CR/2
R/2x Y
Dr. Ahmed H. Madian-VLSI 38
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Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
A
x
Y
2 2 22 6 4
7 4
R R Rpdft C h C
h RC
(6+4h)C2CR/2
R/2x Y
Dr. Ahmed H. Madian-VLSI 39
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Delay Estimation (cont.)
Dr. Ahmed H. Madian-VLSI 40
3 input NAND gate with it’s gate and diffusion capacitances (assuming all nodes are contacted). Estimation at schematic levels will be different if you look at the layouts.
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Layout models
Dr. Ahmed H. Madian-VLSI 41
Good layout minimizes the diffusion area. 3 input NAND shown here, shares one diffusion contact, thus lowering the output capacitance by 2C. Contact diffusions are assumed.
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Dr. Ahmed H. Madian-VLSI 42
Body effect & delay
• If A goes from 0 to 1 while B, C and D are 1, then all the intermediate nodes in the pulldown chain have already been discharged and the top MOSFET sees only a small body effect.
• If D goes from 0 to 1 while A, B and C are 1,
then the intermediate nodes are all one Vt below Vdd and the upper MOSFETs see a larger body effect.
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Dr. Ahmed H. Madian-VLSI 43
Circuit characterization & performance
Delay estimation Simple RC model
Penfield-Rubenstein Model
Delay minimization techniques Transistor sizing
Wiring sizing
Distributed drivers
Driving large loads
Wiring techniques
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Dr. Ahmed H. Madian-VLSI 44
Delay minimization techniques
a b c d
VDD
a
b
c
d
out
Cout
Cab
Cbc
Ccd
VDD
Vin Vout
2/1
1/1 Transistor sizing for minimum delay
Each Series transistors has
(W/L) = 3(W/L)basic inverter.
each parallel transistors has (W/L) = (W/L)basic inverter
Transistor sizing
Basic inverter
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Wire sizing
Wire length is determined by layout architecture, but we can choose wire width to minimize delay.
width can vary with distance from driver to adjust the resistance which drives downstream capacitance.
Dr. Ahmed H. Madian-VLSI 45
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Optimal wire sizing
Widening the wire reduces the resistance, but increases its capacitance.
Wire with minimum delay has an exponential taper.
Optimal tapering improves delay by about 8%.
Can approximate optimal tapering with a few rectangular segments.
Dr. Ahmed H. Madian-VLSI 46
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Tapering of wiring trees
Different branches of tree can be set to different lengths to optimize delay.
Dr. Ahmed H. Madian-VLSI 47
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Spanning tree
A spanning tree has segments that go directly between sources and sinks.
Dr. Ahmed H. Madian-VLSI 48
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Dr. Ahmed H. Madian-VLSI 49
Distributed driver
Decrease output load capacitance
Undistributed : Cload = 8Cg Distributed: Cload = 6Cg
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Dr. Ahmed H. Madian-VLSI 50
Driving large loads
If large loads have to be driven, the delay may increase drastically. Large loads are output capacitances, clock trees, etc.
CLoad
td = tinv (CL/CG) Where tinv=is the average delay of a minimum-sized inverter driving another minimum sized inverter, CL = load capacitance& CG = gate capacitance
CL= 1000CG, then td = 1000.tinv
A possibility to reduce the delay, is to use a sequence of n scaled inverters, but not the optimum delay:
td = tinv (40/1)+ tinv (200/40) + tinv (1000/200)= 50tinv
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Dr. Ahmed H. Madian-VLSI 51
Driving large loads (cont.)
We may decrease the delay by using larger transistors to decrease the resistance. Scaling transistors by factor S results in:
S
RR
L
WS
L
W
scaledscaled
normalscaled
tr = 2.2Rscaled (Cin+ Cload)
But scaling the transistor also affects the input capacitance of the transistor:
Cin,scaled = S . Cin
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Dr. Ahmed H. Madian-VLSI 52
Driving large loads (cont.)
The problem is if input signal is placed at inverter 1 what’s the number of stages N and
the scaling factor S that will minimize the time needed for the signal to reach Cload
CLoad
...Cin 1 2 3 N-1 N
(W/L) S(W/L) S2(W/L) S
N-2(W/L) S
N-1(W/L)
reference
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Dr. Ahmed H. Madian-VLSI 53
Driving large loads (cont.)
td = t1+t2+t3+…+tN
CLoad
...Cin 1 2 3 N-1 N
(W/L) S(W/L) S2(W/L) S
N-2(W/L) S
N-1(W/L)
reference
C2= SC1C3=S
2C1C1
C4=S3C1
CN=sN-1
C1
R1 R2=R1/S R3=R1/S2 RN-1=R1/S
N-2 RN=R1/SN-1
)(
...
11
11
11
1
2
11
4
3
11
3
2
11
2111
CSRNt
CSS
RCS
S
RCS
S
RCS
S
RCS
S
RSCRt
d
N
N
N
Nd
td = R1C2+ R2C3 + R3C4 +…+RN-1CN+RNCload
Cload = SN C1
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Dr. Ahmed H. Madian-VLSI 54
Driving large loads (cont.)
CLoad
...Cin 1 2 3 N-1 N
(W/L) S(W/L) S2(W/L) S
N-2(W/L) S
N-1(W/L)
reference
C2= SC1C3=S
2C1C1
C4=S3C1
CN=sN-1
C1
R1 R2=R1/S R3=R1/S2 RN-1=R1/S
N-2 RN=R1/SN-1
)(
ln
ln
ln
ln
)(
111
1
1
11
CSRS
C
C
t
S
C
C
N
CSC
CSRNt
Load
d
Load
NLoad
d
For minimum delay, dtd/dS = 0; this yields, S = e =2.71
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Dr. Ahmed H. Madian-VLSI 55
Example
we want to drive a load capacitor of value CL = 10pF. The input stage is defined as C1=20fF and has k1=200µA/V2. calculate the number of stages N to minimize the delay.
21.6)500ln()ln(
)1020
1010ln(
)ln(
ln15
12
1
e
x
x
S
C
C
N
Load
We will select N = 6 to obtain non-inverting chain
solution
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Dr. Ahmed H. Madian-VLSI 56
Check the web site for Assignment 3.
Due date next Saturday.
2nd assignment
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Refs.
David Harris, Logical effort lecture notes, Hurvey mid college, 2004.
CMOS VLSI Design, 4th edition
Introduction to VLSI, 2nd edition
Dr. Ahmed H. Madian-VLSI 57