Michael Traxler, GSI 120120723
TRB3 and Come & Kiss: statusTRB3 and Come & Kiss: status
OutlineOutline
• TRB3 status• Come & Kiss: FEE
– Motivation and concept– CBM-RICH-FEE1– PANDA-DIRC-FEE1
• Live Demonstration
Michael Traxler, GSI 220120723
TRB3: Assembled ModuleTRB3: Assembled Module
Michael Traxler, GSI 320120723
StatusStatus
• 30 modules produced– Samtec connector again hard to solder
• 20 more will be ordered• TDC:
– 48 channels per FPGA, single edge– 64 is the aim
• Used succesfully in several beam times at Mainz• GbE slow control and readout: functional (not
finished)• Integrated Central Trigger System: Bachelor work in
Frankfurt
Michael Traxler, GSI 420120723
TRB3 Setup ExamplesTRB3 Setup Examples
PCtrbnetd
Net
TRB3
GbE
Up
to 2
4 S
PF
s /
800I
/Os
Up to 256 ch. TDC
48V
Trigger/Clock
CBM-RICH-FEE1N-times
ComplexCTS
PANDA-DIRC-FEE
SimpleCTS
Michael Traxler, GSI 520120723
Come & Kiss: Complex Commercial Come & Kiss: Complex Commercial Elements and Keep It Small and SimpleElements and Keep It Small and Simple
MotivationMotivation• Using commercial off the shelf FPGAs as FEE
– Easily available, industrial quality design, package and documentation
– Upgrade included (new silicon on the roadmap of the vendor)
– Vendor independent
How to reach that?How to reach that?– “misuse” of digital FPGAs in the asynchronous and
analoge domain for– Precise Time to Digital Conversion (TDC)– Employing FPGAs as discriminators, ADC and QDC
adding a minimal number of external components
Michael Traxler, GSI 620120723
Front End Electronics in FPGAs: ADCFront End Electronics in FPGAs: ADC
• Include more of the FEE inside the FPGA– Multichannel discriminators not easily available: size– Discriminators → LVDS receivers in the FPGA
• ADC: generate ramp on reference pin, measure time until ref. crosses signal– 10bit ADC, 50MSPS → 20ps time resolution– Advantage: many channels in FPGA (one ramp
generator), no data transfer to the FPGA, low power
Michael Traxler, GSI 720120723
Front End Electronics in FPGAs: QDCFront End Electronics in FPGAs: QDC
• Charge measurement– Modified Wilkinson ADC (W.Koenig and Krakow-group)
• Integrate input signal: capacitor• Discharge via current source → fast crossing of zero• Measure time to reach zero ~ Q
Michael Traxler, GSI 820120723
QDC: First ResultsQDC: First Results
• First results with offline correction: 0.2% charge resolution, dynamic range: 50– Applications:
Calorimeter, ...
Maximum input: 2mA peak, close to saturationIntegrator Discr.: Width ca. 100ns
Input:1mA peakIntegrator Discr.Width ca. 68ns
Prototype Board (4 channels) for TRB 2
73 mm
LVDS Receiver, Driver for TRB
Size determined by connectors and TRB 2 infrastructure
Michael Traxler, GSI 920120723
First ApplicationsFirst Applications
• Many FAIR experiments: PANDA-DIRC and CBM-RICH: (MCP-)PMT FEE + readout– Example: 64 channel PMT ToT-FEE + TDC + DAQ– Amplifier: MMIC BGA2803– 5cm x 16cm
Michael Traxler, GSI 1020120723
First Experiences with CBM-RICH-FEE1First Experiences with CBM-RICH-FEE1
• TDC + DAQ: plug and play• Discriminators:
– Minumum differential voltage: roughly 20mV– Spread from channel to channel: <8mV
• Amplifiers:– MMICs from NXP: BGA2803 etc.– 20dB amplification, 2-3GHz bandwidth– Oscillate when >8 are equipped on PCB– Solution: reduce bandwidth with capacitor at input– Still a low amplitude oscillation on output, but usable– Needs improvement: other amplifiers?
• Test-setup for single photons in Wuppertal this week, beamtime in November
Michael Traxler, GSI 1120120723
PANDA-DIRC1: in preparationPANDA-DIRC1: in preparation
• 16 channels• Correct microwave design
(thanks to Samuel)• MachXO2-4000 for
– Discrimination– LVDS drivers– DAC: PWM + low pass filter– No ext. clock, no ext. flash, one
supply voltage!• LVDS signals go to TRB3 for
TDC measurement• 2600 channels
Michael Traxler, GSI 1220120723
Live DemonstrationLive Demonstration
• Hopefully works....
Michael Traxler, GSI 1320120723
TRB3 and Come & Kiss: statusTRB3 and Come & Kiss: status
Thank you for your attention!
Michael Traxler, GSI 1420120723
• Backup slides start here