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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 1
Topic IIaInstruction Set Architecture and
MIPS
Introduction to Computer Systems Engineering
(CPEG 323)
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 2
Reading List
• Slides: Topic2a
• Henn & Patt: Chapter 2
• Other papers as assigned in class or homeworks
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MIPS R4000 Processor Internal Block Diagram
04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 4
System
Control
S-Cache Controll
er
Data Cache
P-Cache Controlle
r
Instruction Cache
Exception / Control Registers
Memory Management Registers
Translation Look-Aside Buffer
CPU Registers
ALU
Load Aligner / Store Driver
Integer Multiplier / Divider
Address Unit
PC Incrementer
FPU Registers
Pipeline Bypass
FP Multiplier
FP Divider
FP add convert sq root
Pipeline Control
CP0 CPU FPU
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Registers
• 32 regs with R0 = 0
• Reserved registers : R1, R26, R27.
• Special usage:R28: pointer to global area
R29: stack pointer
R30: frame pointer
R31: return address
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Standard Register Conventions
• The 32 integer registers in the MIPS are “general-purpose” –
any can be used as an operand or result of an arithmetic op
• But making different pieces of software work together is
easier if certain conventions are followed concerning which
registers are to be used for what purposes.
• These conventions are usually suggested by the vendor and
supported by the compilers
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 7
Register Conventions in the MIPS
$zero 0 Constant 0
- 1 (Reserved for assembler)
$v0-$v1 2-3 Return values/expression eval
$a0-$a3 4-7 Args to functions
$t0-$t9 8-15, 24-25 Temporaries (NOT SAVED)
$s0-$s7 16-23 Saved values
- 26-27 (Reserved for OS kernel)
$gp 28 Global pointer
$sp 29 Stack pointer
$fp 30 Frame pointer
$ra 31 Return address
Names Regs Purpose
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MIP
S r
egis
ters
an
d u
sag
e co
nve
nti
on
Register name Number Usagezero 0 Constant 0
at 1 Reserved for assemblerv0 2 Expression evaluation and results of a functionv1 3 Expression evaluation and results of a functiona0 4 Argument 1a1 5 Argument 2a2 6 Argument 3a3 7 Argument 4t0 8 Temporary (not preserved aross call)t1 9 Temporary (not preserved aross call)t2 10 Temporary (not preserved aross call)t3 11 Temporary (not preserved aross call)t4 12 Temporary (not preserved aross call)t5 13 Temporary (not preserved aross call)t6 14 Temporary (not preserved aross call)t7 15 Temporary (not preserved aross call)s0 16 Saved temporary (preserved across call)s1 17 Saved temporary (preserved across call)s2 18 Saved temporary (preserved across call)s3 19 Saved temporary (preserved across call)s4 20 Saved temporary (preserved across call)s5 21 Saved temporary (preserved across call)s6 22 Saved temporary (preserved across call)s7 23 Saved temporary (preserved across call)t8 24 Temporary (not preserved aross call)t9 25 Temporary (not preserved aross call)k0 26 Reserved for OS kernelk1 27 Reserved for OS kernelgp 28 Pointer to global areasp 29 Stack pointerfp 30 Frame pointerra 31 Return address (used by function call)
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 9
MIPS Operations
• Load/Store
• ALU ops
• Branches/Jumps
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 10
MIPS Instruction Formats
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
op rs rt address
6 bits 5 bits 5 bits 16 bits
op address
6 bits 26 bits
R-Format
I-Format
J-Format
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Here is the meaning of each name of the fields in MIPSinstructions:
• op: operation of the instruction• rs: the first register source operand• rt: the second register source operand• rd: the register destination operand; it gets the
result of the operation• shamt:shift amount • funct: function; this field selects the variant of the
operation in the op field
op rs rt functrd shamt6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
MIPS fields are given names to make them easier to discuss:
Machine Representation of MIPS InsrtuctionsMachine Representation of MIPS Insrtuctions
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ALU ops
• R-type:
ADD R1,R2,R3
effect: R1= R2 + R3
• Example (in MIPS assembler form):
ADD $t0, $s1, $s2
Decimal representation: 0 17 18 8 0 32Decimal representation: 0 17 18 8 0 32
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Machine representation (cont’d)
Decimal representation
0 17 18 328 06 bits 5 bits 5 bits 5 bits 5 bits 6 bits
000000 10001 10010 10000001000 000006 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Binary representation:Binary representation:
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Integer Multiply and Divide in MIPS
• Multiplying two 32-bit numbers can result in up to 64 bits
• Integer division creates a quotient and remainder
• MIPS has two special regs: hi and lo
- Multiply results: lower bits go to lo, upper to hi
- Divide results: quotient goes to lo, remainder to hi
* Use extra ops (such as mflo) to move lo & hi to GPRs.
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 16
Data Transfer Instructions
• I-type (base + 16 bit offsets)
op rs rt address6 bits 5 bits 5 bits 16 bits
Example;lw t0, 8 ($s3) --- # Temporary reg t0 gets A[8]
Note: s3 stores the start address of array A
Also, rs is the base register ($S3 in this case – also called index register), rt (in this case $t0) stores the result (as destination register).
basebase destdest offsetoffset
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 17
MIPS Does A=(B+C)+(D+E)
Assembly
lw $8, 48($0)
lw $9, 76($0)
add $8, $8, $9
lw $9, 20($0)
lw $10, 32($0)
add $9, $9, $10
add $8, $8, $9
sw $8, 100($0)
op rs rt rd sh. Ft.
35 0 8 48
35 0 9 76
0 8 9 8 0 32
35 0 9 20
35 0 10 32
0 9 10 9 0 32
0 8 9 8 0 32
43 0 8 100
An Example An Example
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 18
Branches
• In most processors, the “Program Counter” (PC) holds the
address of the next instruction; fetch from M[(PC)]
• Normally, after an instruction is finished, the CPU adds n to the
PC, where n is the number of bytes in the instruction.
• Branches allow a program to start fetching from a different
place.
• Branches are used to implement all the control-flow commands
of high-level languages, such as if-then-else, for, switch, etc.
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Branch Classification
Two basic types of branches:
Unconditional: Always jump to the specified address
Conditional: Jump to the specified address if some condition
is true; otherwise, continue with the next instruction
Destination addresses can be specified in the same way as
other operands (combination of registers, immediate
constants, and memory locations), depending on what is
supported in the ISA.
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Branch Compilation Example
Compile the following:
if ( i == j)
f = g + h;
else
f = g – h;f = g + h
i == j?
f = g - h
i = j i j
Exit:
Else:
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If-Then-Else in MIPS
Assume f,g,h,i,j in R8-R12 (respectively)
bne $11, $12, Else # Branch if i<>j
add $8, $9, $10 # f = g + h;
j Exit # Jump to Exit
Else: sub $8, $9, $10 # f = g – h;
Exit: … # Code after if
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 22
Observation on Branches
• Most conditional branches go a short and constant
distance
• Fancy addressing modes not often used
• No use for auto-increment/decrement
So in keeping with the RISC philosophy of simplicity, MIPS
has only a few basic branch types.
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MIPS Branch Types
Conditional branch: beq/bne reg1, reg2, addr
- If reg1 =/ reg2, jump to PC + addr (PC-relative)
Register jump: jr reg
- Fetch address from specified register, and jump to it
Unconditional branch: j addr
- Always jump to addr (use “pseudodirect” addressing)
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 24
Generating Branch Targets in MIPS
Memory
Word
op rs rt Address
PC +
Memory
Word
op Address
PC :
4 PC-relative addressing
5 Pseudodirect addressing
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Branch Instructions
• Conditional branches- beq R1, R2, L1 # if R1 = R2 go to L1
- bne R1, R2, L1 # if R1 =\= R2 go to L1
These are R-type instructions
• Unconditional branchesJR R8 # Jump based on register 8
• Test if < 0 sltR1, R16, R17 # R1 gets 1 if R16 < R17
(slt: set-less-than)
bne R1, 0, less # branch to less if R1 =\= 0
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 26
Compiling Other Control Statements
Loops:
• for, while: test before loop body; jump past loop body if
false
• Do: test condition at end of loop body; jump to beginning if
true
Switch: (called “case” statements in some other languages)
• Build a table of addresses
• Use jr (or equiv. In non-MIPS processor)
• Be sure to check for default and unused cases!
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 27
Switch Compilation Example
Compile the following:
switch (k) {
case 0: f = f + 1; break;
case 1: f = f – 2; break;
case 3: f = -f; break;
}
Note the gap (case 2);
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 28
Switch Body in MIPSL0: addi $8, $8, 1 add immed. 1 to r8 (f)
j Exit jump to Exit (break)
L1: subi $8, $8, 2 subtract imm. 2 from r8
j Exit Another break
L3: sub $8, $0, $8 f = 0 - f
j Exit Another break
Build the lookup table in memory:
address of L0
address of L1
address of Exit
address of L3
1000
1004
1008
1012
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 29
Switch Compiled for MIPS
(Assume k in r13)
slti $14, $13, 0 # set r14 if r13 lt 0
bne $14, $0, Exit # Go to Exit if k < 0
slti $14, $13, 4 # set r14 if k < 4
beq $14, $0, Exit # Go to Exit if k 4
add $14, $13, $13 # r14 = 2*k
add $14, $14, $14 # r14 = 4*k
lw $14, 1000 ($14) # Base of table at 1000
jr $14 # Jump to the address
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 30
Instructions Supporting Procedure Calls
• Jump and linkjal procedure address
note: return address is stored in R31
• Return
jr R31
• Saving return address on stackR29 is used as stack pointer
• Parameter passingR4 ~ R7 are used for these
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 31
Other MIPS Addressing Style
• Constant or immediate operands
lw R24, AddrConstant4(0)
addi R3, R4, 5 (I type)
constants are 16-bit long
lui R8 255 load-upper-immediate
• J-type
J 10000 # goto location 10000
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 32
MIPS operands
MIPS assembly languageCategory Instruction Example Meaning Comments
Arithmetic add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registerssubtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers
Data transfer load word lw $s1,100 ($s2) &s1 = Memory [$s2 + 100] Data from memory to registerstore word sw $s1,100 ($s2) Memory [$s2 + 100] = $s1 Data from register to memorybranch on equal beq $s1, $s2, L if ($s1 == $s2) go to L Equal test and branchbranch on not bne $s1, $s2, L if ($s1 != $s2) go to L Not equal test and branch
Conditional branch equalset on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else Compare less than: for beq, bne
$s1 = 0jump j 2500 go to 10000 jump to target address
Unconditional jump jump register jr $ra go to $ra For switch, procedure returnjump and link jal 2500 $ra = PC + 4; go to 1000 For procedure call
Name Example Comments$s0-$s7, $t0-$t9, Fast locations for data. In MIPS, data must be in registers to perform
32 registers $zero, $a0-$a3, $v0- arithmetic. MIPS register $zero always equals 0. $gp (28) is the global$v1, $gp, $fp, $sp, $ra pointer, $sp(29) is the stack pointer, $fp (30) is the frame pointer, and $ra
(31) is the return address.Memory [0], Accessed only by data transfer instructions. MIPS uses byte addresses, so
230 memory words Memory [4],…, sequential words differ by 4. Memory holds data structures, such as arrays,Memory[42949672920 and spilled register, such as those saved on procedure calls.
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 33
MIPS machine language
Name Format Example Commentsadd R 0 18 19 17 0 32 add $s1, $s2, $s3sub R 0 18 19 17 0 34 sub $s1, $s2, $s3lw I 35 18 17 100 lw $s1,100 ($s2)sw I 43 18 17 100 sw $s1,100 ($s2)beq I 4 17 18 25 beq $s1, $s2, 100bne I 5 17 18 25 bne $s1, $s2, 100slt R 0 18 19 17 0 42 slt $s1, $s2, $s3j J 2 2500 j 10000 (see section 3.8)jr R 0 31 0 0 0 8 jr $rajal J 3 2500 jal 10000 (see section 3.8)field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructins 32 bitsR-format R op rs rt rd shamt funct Arithmetic instruction formatI-format I op rs rt address Data transfer, branch format
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 34
Function Calls in the MIPS
• Function calls an essential feature of programming
languages
- The program calls a function to perform some task
- When the function is done, the CPU continues
where it left off in the calling program
• But how do we know where we left off?
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 35
Calling a Function in the MIPS
• Use the jal (“jump and link”) instruction
• jal addr just like “ j addr “ except
- The “return address” (PC) + 4 placed in R31
- This is the address of the next instruction after the jal
- Use jr $31 to return
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 36
Call ExampleCaller Callee
add $4, $0, 1000 F: lw $6, 0($4)
add $5, $0, 1200 lw $7, 0($5)
add $1, $0, 1 sw $6, 0($5)
sw $1, 0($4) sw $7, 0($4)
add $1, $1, $1 jr $31
sw $1, 0 ($5)
jal F
sub $1, $1, $2
What does F do?
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 37
Difficulties with Function Calls
• This example works OK. But what if:
- The function F calls another function?
- The caller had something important in regs R6
and/or R7?
- The called function calls itself?
• Each version of a function should have its own copies
of variables
• These are arranged in a stack, as a pile of frames.
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04/20/23 \course\cpeg323-08F\Topic2a-323.ppt 38
Stack Example
Assume function A calls B, which calls C. Function C calls
itself once:
A’s varsstart A
A’s varsA calls B
A’s varsB calls C
A’s varsC calls D
B’s vars B’s varsC’s vars
B’s varsC’s varsD’s vars