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PowerPoint Slidesto accompany
Digital Principles and DesignDonald D. Givone
Chapter 8Algorithmic State Machines
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Partitioning of a digital system.Figure 8.1
8-1
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Model of an algorithmic state machine.Figure 8.2
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Blocks define states
Transition & output logic
contained within
Compare with Mealy/Moore
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Timing of an algorithmic state machine.Figure 8.3
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Example ASM Block
State box
decision boxConditionaloutput box
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The state box.Figure 8.4
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The decision box. (a) Symbol. (b) Alternate symbol.Figure 8.5
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The conditional output box.Figure 8.6
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Example of an ASM block and its link paths.Figure 8.7
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Two equivalent ASM blocks.
Two blocks are equivalent if
- same state output variables named in state box
- for every setting of input values
- the same next state is chosen
- the same set of output variables are named in the set of conditional
output boxes traversed
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Two equivalent ASM blocks. (a) Using a single decision box.(b) Using several decision boxes.Figure 8.9
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Two equivalent ASM books blocks. (a) Parallel decisionboxes. (b) Serial decision boxes.Figure 8.10
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Invalid ASM block having nonunique next states.Figure 8.11
Both exits selected when
both inputs are 1
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Looping. (a) Incorrect. (b) Correct.Any closed loop must contain at least one state box
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ASM chart for a mod-8 binary counter.Figure 8.13
State output isstate code
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ASM chart for a mod-8 binary up-down counter.
Input Icontrolsdirection
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Moore sequential network. (a) State diagram. (b) ASM chart.Figure 8.15
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Mealy sequential network. (a) State diagram. (b) ASM chart.Figure 8.16
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ASM chart to recognize the sequence x1x2 = 01,01,11,00.Figure 8.17
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Binary multiplication. (a) Pencil-and-paper approach. (b) Add-shift approach.Figure 8.18
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Architecture for a binary multiplier.Figure 8.19
Sum always computed,
ADD tells A,C to load
SR shifts C A M right
start
Multiplier bit
finished
INIT loads M,B, Counter, clears C
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ASM chart for a binary multiplier.Figure 8.20
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Assigned ASM Table
Note grouping of link paths
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An ASM chart to illustrate state assignment.Figure 8.21
A ->A,B
B->A,C,D
C->C,D
D->E
E->A
3 state bits needed
Assign codes to each state
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A minimum state locus assignment for the ASM chart of Fig.8.21. (a) State-assignment map. (b) State locus.Figure 8.22
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Karnaugh map for simplifying the function of Table 8.1b.Figure 8.23
+
1Q
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ASM Excitation Table defines FF input equations
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Using variable-entered Karnaugh maps to obtain a discrete-gate realization with clocked D flip-flops
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Using variable-entered Karnaugh maps to obtain a discrete-gate realization with clocked D flip-flops for the ASM chart ofFig. 8.21.Figure 8.25
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Using variable-entered Karnaugh maps to obtain a discrete-gate realization with clocked JK flip-flops for the ASM chartof Fig. 8.21.
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Assignment of inputs to a multiplexer for each excitation andoutput function.
One mux per function
Each input function correspondsto cell function in variable-entered K-map
x + x 1 2
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Multiplexer realization with clocked D flip-flops for the ASMchart of Fig. 8.21.
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Fragments of ASM charts illustrating problems associatedwith asynchronous inputs. (a) Transition race. (b) Outputrace.Figure 8.31
* Meansasychronousw.r.t. ASMclock
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Using a clocked D flip-flop to synchronize an asynchronousinput.Figure 8.32