Download - Timer
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Zilog Encore! XP Microcontroller
Timer
Timer Block Diagram
© Zilog
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Hardware timers
• Count-up registers that can operate in the background w/o CPU
control (after init)
• More predictable timing than software loops
• Can generate interrupt when count-up complete
• Uses
• Periodic interrupts
• Delays
• Time intervals
• Count pulses
Prescaler
• Divides the frequency by powers of 2
• E.g. for N=64, 18.432MHz crystal / N = 288 KHz
• N ranges from 1 to 128.
To 16-bitmain counter
Prescaler
System clock
Timer input
TxCTL[5:3]
One-shot Counting
• Each time prescaler reaches end of count, T0 counter increments by 1
• When counter reaches value in reload register
• INT5 is generated• Counter is reset to 1• Counting stops
T0RL = 5; T0RH = 0;
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1-2-3-4-5-1
INT5 generatedCounter started
T0L = 1; T0H = 0;
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Continuous Counting
• Each time prescaler reaches end of count, T0 counter increments by 1
• When counter reaches value in reload register
• INT5 is generated• Counter is reset to 1• Counting continues
T0RL = 5; T0RH = 0;
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1-2-3-4-5-1-2-3-4-5
INT5 generatedCounter started
T0L = 1; T0H = 0;
Sample countdown
• Given: 18.432 MHz uC clock
• Want: 2ms delay
• Choose: prescaler to 128
• Timer/counter should be 0.002/(128/18,432,000) = 288
• Actual delay is1/(18,432,000/128/288) = 2.00ms
Counter Range
• Assume 18.432 MHz clock
• Largest delay possible
65536 * 128 / 18.432MHz = 455 msec
• How to make longer intervals
• Use software counter on top of hardware counter
• Can cascade two timers
• Smallest possible interval
1 / 18.432 MHz = 54 nsec
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Timer inputs and outputs
• Alternate function of some GPIO pins
• PA0: T0IN, Timer 0 Input
• PA1: T0OUT, Timer 0 Output
• PC0: T1IN, Timer 1 Input
• PC1: T1OUT, Timer 1 Output
• PC6: T2IN, Timer 2 Input
• PC7: T2OUT, Timer 2 Output
• PD0: T3IN, Timer 3 Input
• PD1: T3OUT, Timer 3 Output
Timer register map
…
Timer 0 Registers
Timer 1 RegistersTimer 2 Registers
Timer 3 Registers…
F18-F1FhF10-F17hF08-F0FhF00-F07h
…High byte (T0H)
Low byte (T0L)
Reload high byte (T0RH)Reload low byte (T0RL)
PWM high byte (T0PWMH)PWM low byte (T0PWML)
Reserved
Control (T0CTL)…
F03hF02hF01hF00h
F07hF06hF05hF04h
Setting it up
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Timer control register
Timer 0 Control Register (T0CTL)
TEN TPOL PRES TMODE
TEN: Timer Enable•0: disabled
•1: enabled
TPOL: Timer Polarity
•Controls T0OUT (timer output pins)
•Function depends on timer mode used•E.g. in one-shot and continuous modes
•When timer disabled, timer output pin is set to TPOL bit value
•When timer enabled, timer output pin is
toggled upon timer reload
Timer control register…
Timer 0 Control Register (T0CTL)
PRES: Prescaler•000: Divide by 1
•001: Divide by 2•010: Divide by 4
•011: Divide by 8
•100: Divide by 16•101: Divide by 32
•110: Divide by 64
•111: Divide by 128
TMODE: Timer Mode•000: one-shot
•001: continuous•010: counter
•011: PWM
•100: capture•101: compare
•110: gated
•111: capture/compare
TEN TPOL PRES TMODE
Timer/counter 0, T0H/T0L
T0H7 T0H6 T0H5 T0H4 T0H3 T0H2 T0H1 T0H0
Timer 0 High Byte (T0H)
T0L7 T0L6 T0L5 T0L4 T0L3 T0L2 T0L1 T0L0
Timer 0 Low Byte (T0L)
© Zilog
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Timer 0 reload, T0RH/T0RL
T0RH7 T0RH6 T0RH5 T0RH4 T0RH3 T0RH2 T0RH1 T0RH0
Timer 0 Reload High Byte (T0RH)
T0RL7 T0RL6 T0RL5 T0RL4 T0RL3 T0RL2 T0RL1 T0RL0
Timer 0 Reload Low Byte (T0RL)
© Zilog
Timer interrupts
• IRQ Assignments
• INT3: Timer 2
• INT4: Timer 1
• INT5: Timer 0
• INT19: Timer 3
Interrupt Request 0 Register (IRQ0)
T2I T1I T0I U0RXI U0TXI I2CI SPII ADCI
0: No interrupt request pending
1: Interrupt request pending
Interrupt Request 2 Register (IRQ2)
T3I U1RXI U1TXI DMAI PC3I PC2I PC1I PC0I
Timer interrupts (priority and enable)
Interrupt 0 Enable High Register (IRQ0ENH)
T2ENH T1ENH T0ENH U0RENH U0TENH I2CENH SPIENH ADCENH
Interrupt 0 Enable Low Register (IRQ0ENL)
T2ENL T1ENL T0ENL U0RENL U0TENL I2CENL SPIENL ADCENL
Interrupt 2 Enable High Register (IRQ2ENH)
Interrupt 2 Enable Low Register (IRQ2ENL)
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Exercise: Pulse width modulation
• How to control LED brightness?Vary it’s duty cycle
• PWM
• used to control DC motors, light dimmers
• allows digital outputs to vary an analog quantity without a Digital-to-Analog Converter (DAC)
Low duty cycle = dim LED
ON OFF
High duty cycle = bright LED
ON OFF
0x008F
0x0200
0x0300
MEMSMicroElectroMechanical Systems
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Accelerometer
ADXL 213
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Block Diagram
Formula of A(g)
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Capturing Signal from Accelerometer
• T1 – duty cycle
• GATED MODE
• T2 – frequency
• CAPTURE / COMPARE MODE
Gated Mode
TMODE: Timer Mode000: one-shot
001: continuous010: counter
011: PWM100: capture
101: compare110: gated
111: capture/compare
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Capture / Compare Mode
TMODE: Timer Mode000: one-shot
001: continuous010: counter
011: PWM100: capture
101: compare110: gated
111: capture/compare
Demo / Exercises
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References
• Zilog Z8F64xx Product Specification: PS0199
• Designing with the Z8 Encore! Microcontroller by Luis G. Sison, Ph.D. and Osmonn T. Burgos, M.S.
• Slimboard Layout and Diagram by Mike Abundo of UP EEE and E-Gizmo