GIEE, NTU 1The EDA Lab
Etron Project:Placement and Routing for Chip-Package-
Board Co-Design
Progress Report
Jia-Wei Fang, Kuan-Hsien Ho, and Yao-Wen Chang
The Electronic Design Automation Laboratory
Graduate Institute of Electronics Engineering
National Taiwan University
June 5, 2008
2
Outline
․ Introduction
․ Problem Formulation
․ Placement and Routing Algorithm
3
Introduction
․ Cross sections of a die, a BGA package, and a PCB
DieBonding wireFinger
BGAPinBump ball
PCB
PCB wire
Package wire
Metal layers
Top metal layer
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Chip-Package-Board Co-Design
․ Advantages: Give higher flexibility to design a system Can achieve much higher performance
․ Package planning Determine package size and then place the package on the PCB
․ Package routing Route nets from fingers to bump balls
․ PCB routing Route nets from bump balls to component pins
Die
PackageComponent pins
PCB : Fingers
: Bump balls
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Problem of Chip-Package-Board Co-Design
․ Problem: Given a die with fingers, a placement of components with pins,
the numbers of BGA and PCB metal layers, and a netlist Generate and place the package and then assign signals and
route wires from component pins to fingers via bump balls
․ Objectives Maximize routability Minimize package size, total wirelength, and the number of vias
Die
PackageComponent pins
PCB : Fingers
: Bump balls
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Example
BGA creation and placement
BGA and PCB routing
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Design Flow
Global Routing Detailed Routing
Routing Result Output
No
Yes
Layer Assignment
CPB Placement
Any-Angle RoutingRouting Network Construction
Package and PCB Routing
Bump-Ball Arrangement
Package Placement
Routed & Minimized?
Die (Fingers), Components (Pins)# Layers, Netlist, Design Rules
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Design Flow
Global Routing Detailed Routing
Routing Result Output
No
Yes
Layer Assignment
CPB Placement
Any-Angle RoutingRouting Network Construction
Package and PCB Routing
Bump-Ball Arrangement
Package Placement
Routed & Minimized?
Die (Fingers), Components (Pins)# Layers, Netlist, Design Rules
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Bump-Ball Arrangement
․ Determine package size (can get the minimum rectangle size)
․ # bump balls of (r-1) rings < # fingers < # bump balls of r rings
ring r
ring r-1
Fingers
Bump ball
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Package Placement (1/2)
․ Apply linear programming (LP) to determine the location of the package
․ Step 1: Define legal regions of package placement
2
1
3 4
q
p r
(x1, y1)
(x2, y2)
(xc, yc)
(xp, yp)
xboundary
yboundary
c Package Center
Pin
x=0
y=0
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Package Placement (2/2)
․ Step 2: Formulate LP Objective function: Minimize total wirelength
Min |(xc+xp)-x1|+|(yc+yp)-y1|+|(xc+xp)-x2|+|(yc+yp)-y2|+
|(xc+xp)-x3|+|(yc+yp)-y3|+|(xc+xp)-x4|+|(yc+yp)-y4|
Subject to Package placement in legal regions
xp>xboundary
yp+package width<yboundary
xp>0
yp>0
Min A
A |(x≧ c+xp)-x1|
(A (x≧ c+xp)-x1; A≦-(xc+xp)+x1)
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Design Flow
Global Routing Detailed Routing
Routing Result Output
No
Yes
Layer Assignment
CPB Placement
Any-Angle RoutingRouting Network Construction
Package and PCB Routing
Bump-Ball Arrangement
Package Placement
Routed & Minimized?
Die (Fingers), Components (Pins)# Layers, Netlist, Design Rules
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Global Routing (1/3)
․ Two types of nets Type 1: from a finger to a bump ball Type 2: from a finger to a component via a bump ball
․ Apply network flow to do global routing Multi-sources Single sink
f1
f2
f3
b4
b5
b6
b1
b2
b3
BGAPCB ChipPre-assigned signals Only given a netlist
b
a
c
s2
s1
Use s2 to choose the bump pads for Type 1
t
Netlist: 1, 2, 3
Finger
es1_1
Ball
Pin
1
2
na
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Global Routing (2/3)
․ Two types of nets Type 1: from a finger to a bump ball Type 2: from a finger to a component via a bump ball
․ Apply network flow to do global routing Multi-sources Single sink
f1
f2
f3
b4
b5
b6
b1
b2
b3
Pin
1
2
BGAPCB Chip
g
h
s2
t
Netlist: 1, 2, 3
s1
Finger
Only given a netlist
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Global Routing (3/3)
․ Apply LP to solve the routing network
․ LP formulation: Objective function & constraints
․ Objective function: Minimize total wirelength min Σl(ei_j)ei_j (l(ei_j): length of ei_j)
․ Subject to Capacity of each edge/node (model routing resource)
ei_j cap(e≦ i_j); ni cap(n≦ i); Flow constraint
Σei_j = Σej_k
Routability constraint es1_i = 1
Σes2_bi = # fingers – Σes1_j
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Global Routing Result
1
3
2
1
3
2
Pin
1
2
BGAPCB Chip
Pre-assigned Signals Only given a netlist
Netlist: 1, 2, 3
Finger
Ball
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Layer Assignment (1/2)
․ In global routing, integrate all metal layers into one layer
․ Model the layer assignment as a flow network to distribute nets into each layer after global routing
1
3
2
1
3
2
BGA Chip
Finger
Ball
1
3
2
l
r
Layer 1
Layer 2
ts
Flow network
es_2
es_1 el_t
er_t
e1_l
e2_r
Can only route 2 wires in one layer
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Layer Assignment (2/2)
․ Apply LP to solve the flow network․ Objective function: Minimize total via cost
min Σci_jei_j (ci_j: via cost of ei_j)․ Subject to
Capacity of each metal layer el_t 2; e≦ r_t 2≦
Flow constraint es_1 = 1; es_2 = 1; es_3 = 1 Σei_j = Σej_k
Whole net in the same metal layer A net is composed of two wires p and q ei_l
p = ei_lq; ei_r
p = ei_rq
BGA
PCB
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Detailed Routing
․ The PCB routing does not allow any routing path with an acute angle
The router should check every turning point to avoid an acute angle
Once an acute corner is detected, the two adjacent net segments can be cut off to generate two obtuse angles
Acute angle
Turn
Original routing path
Min. spacing ring
: Pins
: Bump balls
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Differential Pair
․ Implement the proposed algorithm
․ Consider differential pairs Can have better signal integrity
Differential pair
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Preliminary Layout
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Schedule
․ Problem of Chip-Package-Board Co-Design Stage 1 (1/2008 – 4/2008): done
Literature survey Development of a placement and routing
algorithm considering the objectives Stage 2 (5/2008 – 7/2008): almost done
Implementation of the placement and routing algorithm
Stage 3 (8/2008 – 9/2008) Optimization of the objectives
Stage 4 (10/2008 – 12/2008) GUI generation and integration of all functions Paper writing and documentation