ICCD 2006 Mohanty & Kougianos 1
Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates
Saraju P. Mohanty and Elias KougianosVLSI Design and CAD Laboratory (VDCL)
Dept of Computer Science and EngineeringUniversity of North Texas, Denton, TX, 76203.
Email: [email protected]
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Outline of the Talk
CMOS scaling –Trends and EffectsPower consumption redistribution due to scaling
Components of Power DissipationComponents of Leakage
Gate leakage analysis – Proposed MetricsGate leakage variation with process and design parameters
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CMOS Driven Applications
Almost the entire industrial revolution today is driven by CMOS.
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CMOS Technology Scalingand
Power Dissipation Redistribution
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Scaling Trend – Transistor Count
1967 2007
Increase in Transistor Count per chip
VLSI technology is the fastest growing technology in the human history.
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What is Physically Scaled ? (Gate Length)
Gate length of the transistor has been decreasing with technology scaling.All the other dimensions including gate oxide thickness have been scaled down to support this trend.
Source: Pedram ASPDAC 2004, Osburn IBM JRD Mar2002
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Other Parameters Scaled?
0.51 0.020.2 0.1Channel Length (µm)
5
21
0.2
0.1
0.5
0.20.2
1010Su
pply
and
Thr
esho
ld V
olta
ges
(V)
Vdd
Vth
Tox
Source: Taur IBM JRD MAR 2002
Supply Voltage
Threshold Voltage
Gate Oxide Thickness
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Power Dissipation Components in Nano-CMOS
Source: Weste and Harris 2005
Total Power Dissipation
Static Dissipation Dynamic Dissipation
Sub-threshold current
Tunneling currentTunneling current
Reverse-biased diode Leakage
Capacitive Switching
Short circuit
Contention current
Tunneling currentTunneling current
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Leakages in Nanoscale CMOS
P-Substrate
N+ N+
Source DrainGate
I1 : reverse bias pn junction (both ON & OFF)I2 : subthreshold leakage (OFF )I3 :oxide tunneling current (both ON & OFF)I4 : gate current due to hot carrier injection (both ON & OFF)I5 : gate induced drain leakage (OFF)I6 : channel punch through current (OFF)
I3 , I4
I1
I2I6
I5 Source: Roy Proceedings of IEEE Feb2003
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Power Dissipation: Redistribution
Source: Hansen 2004
Tunne
ling
Dynamic
Sub-
Thre
shol
d
Gate Length
Chronological (Year)
Nor
mal
ized
Pow
er D
issi
patio
n
Phy
sica
l Gat
e Le
ngth
(nm
)
Gate leakage will predominate for sub 65-nm technology.
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Scaling Trends and Effects: Summary
Scaling improves Transistor Density of chipFunctionality on a chip Speed, Frequency, and Performance
Scaling and power dissipationActive power remains almost constantComponents of leakage power increase in number and in magnitude.Gate leakage (tunneling) predominates for sub 65-nm technology.
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Contributions of Our Paperand
Related Research
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Contributions of Our Paper
1. Both ON and OFF state gate leakage are significant.
2. During transition of states there is transient effect is gate tunneling current.
3. New metrics: Itun and Ctun
4. Ctun: Manifests to intra-device loading effect of the tunneling current
5. NOR Vs NAND in terms of Itun and Ctun
6. Study process/design variation on Itun and Ctun
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Contributions of Our Paper(Salient Feature)
A new metric, the effective tunneling capacitanceessentially quantifies the intra-device loading effect of the tunneling current and also gives a qualitative idea of the driving capacity of the logic gate.
How to quantify it at transistor and logic-gate level??
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Gate Capacitance of a Transistor(Intrinsic)
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Gate Capacitance of a Transistor(Tunneling: Proposed)
We propose that transient in gate tunneling current due to state transitions are manifested as capacitances.
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Related Research Works(Gate Leakage Analysis)
Ghibaudo 2004: Characterization and modeling issues of ultra thin oxide devicesMukhopadhyay 2003: Characterization methodology is proposed along with reductionYang 1999: Direct tunneling current and CV measurements in MOS devices used to modelHertani 2005: Provide leakage analysis of NAND, NOR, XOR gates
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Related Research Works
No work characterize both ON and OFFNo work examine the device or a logic gate when it changes stated:
ON OFF or OFF ON
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Analysis in a
CMOS Transistor
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Outline: Transistor Level
Dynamics of gate oxide tunneling in a transistorSPICE model for gate leakageON, OFF, and transition states of a transistorGate leakage in ON, OFF, and transition states of a transistor
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Gate Leakage Components(BSIM4 Model)
Igs, Igd: tunneling through overlap of gate and diffusions Igcs, Igcd: tunneling from the gate to the diffusions via channelIgb: tunneling from the gate to the bulk via the channel
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NMOS Transistor: ON
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NMOS Transistor: OFF
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NMOS Transistor: Transition
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Gate Leakage for a MOS: Iox
Calculated by evaluating both the source and drain components
For a MOS, Iox = (|Igs| +|Igd| +|Igcs| +|Igcd| +|Igb|)
Values of individual components depends on states: ON, OFF, or transition
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NMOS Gate Leakage (For a Switching Cycle)
Fig. 1
Fig. 2
Fig. 3
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NMOS Gate Leakage(Observation and Metrics)
Gate leakage happens in ON state: IONGate leakage happens in OFF state: IOFFGate leakage happens during transition: tun
effC
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NMOS Gate Leakage:
tungcsC tun
gbCtungsC tunCgcd
tuneffC
tungdC
tuneffC
5 components
⎟⎠⎞
⎜⎝⎛−
=
dtdV
IICg
OFFONtuneff
rDD
OFFON tV
II −=
We propose to quantify as:
(for equal rise/fall time)
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NMOS Gate Leakage: Summary
The behavior of the device in terms of gate tunneling leakage must be characterized not only during the steady states but also during transient states.
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Transistor Logic Gate
How do we quantify the same metrics at logic level??State dependent or state independent??
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Analysis in
Logic Gates
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Gate Leakage in 2-input NAND(State Specific)
input 00 input 01 input 10 input 11
I00 I01 I10 I11
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Gate Leakage in 2-input NAND(State Specific)
∑=iMOS
ioxLogicox IStateI,
,, )(
00I 01I
Four different states for 2-input NAND:
11I
)(, StateI Logicox
10I
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Gate Leakage in 2-input NAND(State Independent)
Itun ≡ State Independent average gate leakage current of a logic gate
)(41
11100100 IIIIItun +++=
This is a measure of gate leakage of a logic gate during its steady state.
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Gate Leakage in 2-input NAND(Transient Study)
Input Voltages
Output Voltage
I00 I01 I10 I11
Gat
e C
urre
nt in
indi
vidu
al M
OS
Best Case Worst Case
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Gate Leakage in 2-input NOR (Transient Study)
Output Voltage
Input Voltages
Best Case Worst Case
I00 I01 I10 I11
Gat
e C
urre
nt in
indi
vidu
al M
OS
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Gate Leakage in Logic Gate(Transient Study)
Ctun ≡ Effective tunneling capacitance at the input of a logic gate
⎟⎠⎞
⎜⎝⎛
−=
dtdV
IICin
icictun
logmin
logmax
rDD
icic
tV
II logmin
logmax −
=
We propose to quantify as:
(for equal rise/fall time)
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Effect of Process and
Design ParameterVariation
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Gate Leakage in 2-input Logic Gates (Tox Variation)
Itun (logscale) versus Tox Ctun (logscale) versus Tox
NOR
NANDNOR
NAND
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Gate Leakage in 2-input Logic Gates (VDD Variation)
Itun (logscale) versus VDD Ctun (logscale) versus VDD
NAND
NOR NAND
NOR
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Summaryand
Conclusions
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Gate Leakage in 2-input Logic Gates (Observation)
Both ON and OFF states contribute to gate leakageTransient effect is significant and can be captured via effective tunneling capacitanceItun ≡ State Independent average gate leakage current of a logic gateCtun ≡ Effective tunneling capacitance at the input of a logic gateItun is larger for NORCtun is larger for NAND
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Usefulness of the Proposed Metrics
The metrics allow designers to account for gate tunneling effect in nano-CMOS based circuit designs.Itun - additive to static power consumptionCtun – additive to intrinsic gate capacitance
Clogic = Ctun + Cintrinsic
All three needs to be taken into account for effective total (switching, subthreshold, gate leakage) power optimization
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For more information:http://www.cse.unt.edu/~smohanty