Download - Status of electronics for NuTel prototype
Yuri Velikzhanin([email protected])
NuTel TV meeting, June 13 (Friday), 2003
Status of electronics forStatus of electronics forNuTel prototypeNuTel prototype
Status of electronics forStatus of electronics forNuTel prototypeNuTel prototype
PMT Preamp.
UV filter
Hamamatsu8x8 PMT
16-channelspreamplifier
Trigger
FADC
DAQ
RAM
RAM
PMT Preamp.
UV filter
FADC
Trigger
RAM
RAM
Detector pair
Stop
Stop
32 – channels DCM(Data Collection Module) in cPCI
10 bit x40 MHz
2 RAM x 256 x 16 per channel
Mirror
FPGA
Schematics of new electronicsSchematics of new electronics
Main modifications during last monthMain modifications during last month1. Change design from VME onto Compact PCI (cPCI) due we
need fast readout speed for making a second-level software trigger.
2. Delete all interconnections for trigger signals due we don’t need statistics (uniformity, isotropy…) – there will be around one event per year. Loosing less 1% only!
3. Use two triggers: first-level hardware trigger like logical OR of triggers inside all DCM, and second-level software trigger. One Data collection module processes signals from 4x8 pixels (half of MPMT) from one detector.
4. Use 25nS (one clock) gate for trigger logic due most of signal are inside one clock (from our simulations).
RAM bufferRAM buffer
stop
stopreadout
readout Old version: two cycle buffers per channel with depth 256.
1
2
Marked memory cellsfor readout
256 256
x8
256
FIFO1Kx16
FIFO1Kx16
PCI
Expected layout of DCMExpected layout of DCM
TriggerFPGA
J1
J2
P1
triggertrigger
clock
mainFPGA
mainFPGA
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC ADC ADC
ADC
ADC
ADC ADC
ADC
PLX PCI9054
x2 sides
x2 sides
P2
P3?
Config.CPLD
Flashmemory
LVDS
J3?
LOCAL
BUS
cPCI busconnectors
ClockingClocking/timing
TriggerFPGA
FIFOFPGA
FIFOFPGA
40 MHzoscillator
to ADCto ADC
terminators
80 MHz,40 MHz
dividerreg
reg
80 MHzcomparatorexternal
40 MHz
MUXreg
40 MHzwith good0-1 timeratio
DCM x 32 (200)DCM x 32 (200)
Clock distributormodule
32x2 outputs
GlobalClockingmodule
80 MHz,40 MHz
80 MHzoscillator
80 MHzoscillator
?
~2 km. away
GlobalClockingmodule 80 MHz
oscillator
?
How to calculate N p.e./1 clock
AN
AN+1
15/16AN
Change in amplitude due new photoelectrons:
ΔA = AN+1 – 15/16AN
N = ΔA / gain
ADC Reg. Reg.
Reg.>>4 –
AN AN-1
1/16AN 1/16AN-1 15/16AN-1
Reg.
– Reg.
15/16AN-2
ΔAN-1 = AN-1 – 15/16AN-2
Schematics of firmware (inside FPGA)
ΔA
TriggerTrigger
Time interval for triggerFrom simulation > 90% of signal comes during one ADC clock, so time interval will be one clock – 25 nS. There will be used two thresholds logic:
Reg. Reg.ΔANcomparator
Programmable High-level threshold(individual for every channel)
To trigger logic
Schematics of firmware (inside main FPGA)
TriggerTrigger
comparator
Programmable Low-level threshold(individual for every channel)
Reg.
HLT
LLT
TriggerTrigger
Trigger array of one DCMTrigger array of one DCM
DAQ configurationDAQ configuration
TRIGGER
BRIDGE
D
C
M
CPU
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
BRIDGE
D
C
M
D
C
M
D
C
M
D
C
M
TRIGGER
BRIDGE
D
C
M
CPU
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
D
C
M
BRIDGE
D
C
M
D
C
M
D
C
M
D
C
M
Eth
ern
et
Not fixed (discussable) !!!Not fixed (discussable) !!!
PXI chassis GX7000PXI chassis GX7000
Data flux inside main FPGAData flux inside main FPGA
FIFO1Kx16
12256
12256
12256
12256
12256
12256
12256
12256
data
from
ADC
tolocalbus
x16
FIFO size: if 4 time slots:1024/8/4 = 32 events!But we need to add event number:1024/8/5 = 25 events!
event number
Data flux inside one DCMData flux inside one DCM
TriggerFPGA
J1
J2
P1
mainFPGA
mainFPGA
PLX PCI9054
P2
P3?
Config.CPLD
Flashmemory
LVDS
J3?
LOCAL
BUS cPCI bus
connectors
mainFPGA
mainFPGA
D15-D00
D15-D00
D31-D16
D31-D16
Ch.1-8
Ch.9-16
Ch.17-24
Ch.25-32
D31-D00
Possible data flux inside one chassisPossible data flux inside one chassis
CPU
RAMBank#1
RAMBank#2
RAMBank#3
RAMBank#4
from
cP
CI DMA
DMA
Second-leveltriggerDMA
DMA
to E
ther
net
Schedule for electronicsSchedule for electronics
1. Before August 1: have 2 DCM and 4 new preamplifiers2. August-September: debugging first iteration, hope a final3. October-December: making a final firmware, two Trigger
modules (simple), software…4. January: Mass production5. February – March: Mass debugging + start integration test6. End of March - beginning of April: end of the first period of
NuTel project
(moved ~one month later due cPCI design instead VME)
Problems1. Optics – main problem now2. MPMT – we have only 11 pieces, need 16, could Palermo people
give as some pieces? When? If not – we need to bye. We’ll need its before February.
3. HV power supply is in VME. Already have one (for 8 MPMT), need another one.