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Assignment_3
Timing Analysis
1) Find the false paths in the given design.
For condition: s1 = 0 , s2 = 0;
CKP2 and CKP4 are false pats! T"s false pat depends on
inp"t conditions!
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2) Find the false paths in the given design.?
For sel = 0, CK2 and CK4 are false pats!
#ence for $ario"s conditions te false pat %o"ld depend on %at cloc&
pats %e select!
3) If there is an increase in delay of combo logic, in order to meet timing,hat ill
yo! do? "ive to s!ggestions. #efer the $g!re and anser.
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• 'f te interconnect com(inational logic delay is more, one
can consider inserting (")ers if it can impro$e te
transition and ence te delay!
• *ne can consider "sing a larger cell %ic as larger
dri$ing capacity a$ing te same f"nctionality!
%) Find the ma&im!m cloc' fre(!ency of given design.
Clock period = 10ns
Setup requirement for any flip-flop = 0.5nsHold requirement for any flip-flop = 0.1ns
Clock-to-out delay of any flip-flop = 0ns
Considering skew,
ssume data if required.
Calc"lating ma+im"m pat delay: Ts"FF2- . Tlogic . Tc2/ =0!ns . ns = ! nsT"s ma+im"m cloc& fre/"ency : 1!ns = 1!3 + 105 #6
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)
*ay tr!e or false observing the above $g!re.
TRUE
!imings for datapat"# dder delay# $a%&10 ns', $in & ( ns'
$ultiplier delay# $a% &1) ns', $in &10 ns'$u% delay# ( ns &$a% = $in delay'
C*+ of # ns &$a% = $in delay'
!setup of # * ns &$a% setup'
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!"old of # 1 ns &$in "old time'
ind t"e ma% operating frequency.
The maximum path delay: 3ns(Tc2q(DFF)) + 18ns(Multiplier) + 2ns(Tsu(DFF)) = 23ns
Max Frequency = 123ns = !"3!x1#$% &'