Download - SHUBHAM SHAH(1)
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SHUBHAM [email protected], 8487881848
surendranagar-363001, Gujarat
Career Objective
TO BECOME AN EFFICIENT FULL CUSTOM MASK LAYOUT ENGINEER AND FACE ANYCHALLENGES IN THE FIELD AND LEARN FROM IT. ALSO TO LEARN NEWTECHNOLOGIES COMING IN THE FUTURE AND WORK AS A TEAM IN THE CORPORATEWORLD AND BE AS PRODUCTIVE AS I CAN.
Core Competancy
Full custom CAD tools from MENTOR GRAPHICS, IC STUDIO, PYXIS LAYOUT EDITOR,CALIBRE- LVS DRC.Basic knowledge of semiconductor theories, diodes, BJTs, MOSFETs, CMOS fabricationtechnology, analog circuits.Knowledge of ASIC design flow and its various stages, full custom flow.Basic knowledge of programming languages like C, VERILOG.Keeping in mind design rules, worked on diffrent technologies like 180NM, 90NM, 28NM forCUSTOM LAYOUTS of STANDARD CELLS, ANALOG LAYOUTS AND MEMORY LAYOUTS.Can draw the layouts of any given combinatorial or sequential circuit with given netlist, tomake it LVS and DRC clean, with good floor planning, within area constraints.Knowledge of PARASITIC causing factors in layout and can draw layout with minimumparasitics.Knowledge of DFM issues like ELECTROMIGRATION, ANTENNA EFFECT, ELECTROSTATICDISCHARGE, LATCH UP, and their prevention techniques in layouts.Can draw layouts of STANDARD CELLS in any given technology within given height, PORTPLACEMENT, and DESIRED DRIVE-STRENGTH.Knowledge of device matching techniques like COMMON CENTROID, SYMMETRY,COMPACTNESS, INTER-DIGITIZATION, DISPERSION etc in analog layouts, and can drawmatched layouts.
Education DetailsAdvanced Diploma in ASIC Design - Full Custom 2017 RV-VLSI Design CenterBachelor Degree in Electronics and Communication 2016 L.J.I.E.T, with 6.83 CGPAPUC / 12th 2012 DAYAMAYI MATA HIGH SCHOOL(GSHSEB), with 74.46 %SSLC 2010 DAYAMAYI MATA HIGH SCHOOL(GSHSEB), with 86 %
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Domain Specific ProjectRV-VLSI DESIGN CENTERGraduate Trainee Enggineer Oct-2016 to Oct-2016STANDARD CELLS 90NMDescription
DRAWING THE STANDARD CELL LAYOUTS OF COMBINATORIAL LOGIC LIKE INVERTER,NAND, NOR ETC AND SEQUENTIAL LOGIC LIKE D-FLIP FLOP AND MAKING THEM DRCAND LVS CLEAN.
Tools
IC STUDIO, PYXIS LAYOUT EDITOR, CALIBRE- LVS DRC.
Challenges
DRAWING THE LAYOUT IN THE GIVEN STANDARD HEIGHT OF THE STANDARD CELL.OPTIMIZING THE LAYOUT AREA WITHIN MINIMUN WIDTH AS THE HEIGHT ISCONSTANT.MAKING THE LAYOUT DRC CLEAN, KEEPING IN MIND VARIOUS DESIGN RULES LIKEMINIMUM WIDTH OF POLYGONS, MINIMUM SPACING, MINIMUM ENCLOSURE,EXTENSION ETC.COMING UP WITH A OPTIMIZED LAYOUT WITH SHARING OF THE DRAIN SOURCESWHEREVER REQUIRED, MAKING PROPER CONECTIONS AS PER THE SCHEMATIC ANDFINALLY MAKING THE LAYOUT LVS CLEAN.
RV-VLSI DESIGN CENTERGraduate Trainee Enggineer Nov-2016 to Nov-2016STANDARD CELLS 28NMDescription
DRAWING THE LAYOUTS OF STANDARD CELLS OF COMBINATORIAL LOGIC LIKEINVERTER, NAND, NOR ETC WITH DIFFRENT DRIVING STRENGTHS.
Tools
IC STUDIO, PYXIS LAYOUT EDITOR, CALIBRE- DRC LVS.
Challenges
DRAWING THE LAYOUT IN THE GIVEN STANDARD HEIGHT OF THE STANDARD CELL.OPTIMIZING THE LAYOUT AREA WITHIN MINIMUN WIDTH AS THE HEIGHT ISCONSTANT.DRAWING THE LAYOUT WITH DESIGN RULES OF POLY AND CONTACT GRIDS,HORIZONTAL POLY RULES ETC AND MAKING THE LAYOUT DRC CLEAN.KEEPING THE LAYOUT OPTIMIZED AND SMALL, BY SHARING THE SOURCE DRAINWHEREVER REQUIRED KEEPING IN MIND ALL THE POLY AND CONTACT GRID RULES.
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RV-VLSI DESIGN CENTERGraduate Trainee Enggineer Oct-2016 to Oct-2016180NM LVS TEST CASE EXECUTION.Description
READING THE 180NM DRC, LVS AND SVRF DOCUMENT, UNDERSTANDING IT ANDSOLVING THE LVS ERRORS IN THE GIVEN TEST CASE LAYOUT.
Tools
IC STUDIO, PYXIS LAYOUT EDITOR, CALIBRE- LVS.
Challenges
UNDERSTANDING THE SVRF DOCUMENT AND LVS DOCUMENT FOR 180NM.IDENTIFYING THE COMMON ERRORS LIKE SHORTED NETS, INCORRECT INSTANCES,INCORRECT NETS, PROPERTY ERRORS ETC.IDENTIFYING THE COMMON ERRORS IN THE LAYOUT, ANALYSING THE SOURCENETLIST SCHEMATIC AND THE LAYOUT NETLIST SCHEMATIC, AND FIXING THE ERRORSIN THE LAYOUT THUS MAKING IT LVS CLEAN.
RV-VLSI DESIGN CENTERGraduate Trainee Enggineer Oct-2016 to Oct-2016ANALOG LAYOUT 90NM.Description
DRAWING THE LAYOUT OF ANALOG DEVICE LIKE OP-AMP ACCORDING TO THE GIVENNETLIST AND GETTING IT DRC LVS CLEAN.
Tools
IC STUDIO, PYXIS LAYOUT EDITOR, CALIBRE- DRC LVS.
Challenges
PERFORMING TRANSISTOR FOLDING AND COMING UP WITH A WIDTH OF TRANSISTORWHICH IS A FACTOR OF ALL THE GIVEN TRANSISTOR WIDTH, THUS MAKING THELAYOUT SYMETRIC.COMMING UP WITH AN OPTIMIZED FLOORPLAN FOR ALL TRANSISTOR IN THE DEVICE,ADDING DUMMY TRANSISTOR WHEREVER NEEDED, AND DRAWING A SYMETRICLAYOUT.TRANSISTOR MATCHING WITH VARIOUS MATCHING TECHNIQUES LIKE COMMONCENTROID, DUMMY POLY, DUMMY TRANSISTOR, PLACING TRANSISTOR IN CLOSEPROXIMITY, IDENTICAL FINGER GEOMETRY ETC.
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RV-VLSI DESIGN CENTERGraduate Trainee Enggineer Nov-2016 to Dec-2016MEMORY LAYOUT 28NM.Description
DRAWING THE LAYOUTS OF THE LEAF CELLS OF AN SRAM ACCORDING TO THE GIVENNETLIST AND MAKING THE CONNECTIONS OF THE LEAF CELLS IN THE TOP LEVELBLOCK TO MAKE THE SRAM MEMORY.
Tools
IC STUDIO, PYXIS LAYOUT EDITOR, CALIBRE- LVS DRC.
Challenges
DRAWING THE OPTIMIZED LAYOUT OF THE LEAF CELLS LIKE PRECHARGE, SENSE AMP,DOUT, DIN, CONTROL BLOCK, DECODER ETC ACCORDING TO THE TOP LEVEL ANDPLACING THEIR PINS ACCORDINGLY.DRAWING THE LAYOUT OF ANALOG BLOCK SENSE AMP KEEPING IN MIND DEVICEMATCHING AND PLACING THE PINS OF PRECHARGE SO THAT THEY ALLIGN EXACTLYWITH THE ARRAY CELL BLOCK.MAKING THE CONNECTION OF PINS IN TOP LEVEL BLOCK AND KEEPING THE SRAMLAYOUT AS COMPACT AS POSSIBLE. MAKING THE DRC AND LVS CLEAN FOR THE TOPLEVEL BLOCK WITH DRC RULES.
B.E / B.Tech Academic ProjectL.J.I.E.TSECURITY HAND BELT USING GPS AND GPRSDescription
IF THE USER IS AT ANY ALIEN PLACE OR SENSES ANY DANGER WHEREVER HE/SHE IS,HE CAN PRESS A BUTTON ON THE DEVICE AND CAMERA CAPTURES AN IMAGE WHICHALONG WITH THE LOCATION FROM GPS IS SENT THROUGH GPRS TO A PRE-DECIDEDNUMBER, THUS PROVIDING SECURITY.
Tools
HARDWARES- ARM MICRO-CONTROLLER, CAMERA, GPS MODULE, GPRS MODULE, 16*2LCD SCREEN, VOLTAGE REGULATOR ICS. SOFTWARES- KEIL, FLASH MAGIC.
Challenges
SOLDERING THE CONTROLLER, LCD AND VARIOUS OTHER COMPONENTS ON THEBOARD. DRAFTING A CODE TO BE DUMPED ON THE ARM CONTROLLER TO INTERFACEAND RUN ALL THE COMPONENTS USED. LEARNING THE AT COMMANDS FOR THE GPRSMODULE. MAKING THE BELT COMPACT.
