Download - Serial Communication Interface (SCI) Kevin Stuart Matt Betts March 27, 2007 ME 6405, Sp 07
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Serial Communication Interface (SCI)
Kevin Stuart
Matt Betts
March 27, 2007ME 6405, Sp 07
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Types of communication
2 main types Serial
Telegraph Light Signal
Parallel ISDN line Factory line
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Serial Communication
One line of communication, long string of data
Time
Signal
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Parallel Communication
Many lines of communication, synchronized bursts of data
Time
Transmitter Receiver
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Endianness, how it relates to communication
Big Endian- MSB first, less significant bytes in descending order
Little Endian- MSB last, data in ascending order
Endian type determines how the data is interpreted, and how it should be sent in both serial and parallel communication.
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RS232, SCI, and SPI
RS232- Typical computer COM port SCI- Serial Communication interface, uses
the universal asynchronous receiver/transmitter or UART
SPI Serial peripheral interface, part of Port D.
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Cable Length / Data Transfer Rate Relation
As cable lengths increase, signal quality degrades
As data transfer speed increases, signal quality degrades much faster for increasing length
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Synchronous Communication
Clock speed determines the data transfer rate
Transmitter and receiver use the same clock to keep signal cohesive.
Constantly sending data to maintain clock synchronization, including idle characters.
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Asynchronous Communication
Transmitter and receiver operate independently
No synchronization So no idle characters
HC11 uses this type of communication
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Bit Rate
Number of possible on/off switches per second, based on the clock.
Faster clock, faster bit rate Standard bit rates
Some typical bit rates
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Baud Rate
Number of actual data bits per second Different from Bit Rate because of required
setup bits per word transmitted. Setup bits explained more later
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HC11 SCI registers
5 major registers BAUD $102B SCCR1 $102C SCCR2 $102D SCSR $102E SCDR $102F
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BAUD
0
BAUD register, sets speed TCLR : Clear baud rate timing chain bit SCP : Baud rate pre-scale select bits RCKB : Baud rate clock test bit SCR : SCI baud rate select bits
1234567
Read: 0 0Write: TCLR RCKB SCR1 SCR0SCP00 SCP1 SCR2
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SCCR1
SCCR1 : Serial Communication Interface Control Register 1
R8 : Receive data bit 8 T8 : Transmit data bit 8 M : SCI character length bit WAKE : Wakeup method select bit Bits 0 - 2 & 5 are not used (always 0)
01234567
Read:
Write:
R8T8 M Wake
0 0 0 0
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SCCR2
SCCR2 : Serial Communication Control Register 2
TIE : Transmit interrupt enable bitTCIE : Transmit complete interrupt enable bitRIE : Receive interrupt enable bitILIE : Idle-line interrupt enable bitTE : Transmit enable bitRE : Receive enable bitRWU : Receiver wakeup bitSBK : Send break bit
01234567
Read:
Write:RWU SBKTIE TETCIE RIE ILIE RE
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SCSR
SCI status register TDRE : Transmit data register empty bit TC : Transmit complete bit RDRF : Receive data register full bit IDLE : Idle-line detect bit OR : Overrun error bit NF : Noise flag FE : Framing Error bit Bit 0 is not used (always 0)
01234567
Read:
Write:
TDRE TC RDRF IDLE OR NF FE 0
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SCDR
SCI data register Two separate registers, same address Used to Read the Received data Used to Write the Transmit data R7 - R0 – Read bits T7 - T0 – Write bits
01234567
Read:
Write:R7 R6 R5 R4 R3 R2 R1 R0
T7 T6 T5 T4 T3 T2 T1 T0
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SPCR
Serial Peripheral Interface Control Register SPIE- Serial Peripheral Interrupt Enable
0 = SPI Interrupts disabled 1 = SPI Interrupts enabled
Serial Peripheral System Enable 0 = SPI off 1 = SPI on
DWOM – Port D Wired OR mode Option for Port D pins (PD 5:0) 0 = Normal CMOS outputs (Leave it as 0) 1 = Open Drain outputs
01234567
Read:
Write:SPIE SPE DWOM MSTR CPHA SPR1 SPR0CPOL
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How to set up Serial Communication on the HC11
Set Baud rate using BAUD Set interrupt states using SCCR2 Set data length using SCCR1 Make / Set routines to be jumped to when
interrupt is triggered Read or Write data to the SCDR Note- Data direction register is overridden by
SCI logic
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UART (Universal Asynchronous Receiver/Transmitter)
Beforehand Knowledge Need to know Transmitting speed (and therefore Receiving
speed) Need to know packet construction (# data and formatting bits)
Packet Construction: Start Bit (1 bit) Data Bits (8-9 bits)
Parity Bit (1 bit) …optional Address Marker (1 bit) …optional
Stop Bit (1 bit)
Challenge: Noise
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UART: Start Bit
1 Bit (at beginning of message) Only used due to asynchronous nature
(synchronous Transmitters/Receivers don’t need start/stop bits)
Opposite polarity of data-line’s idle state Idle state for HC11 = all 1’s start bit = 0
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UART: Data Bits
8-9 Bits (in middle of message) Most common mode = 8 data bits (SCCR1, M =
0) Alternative mode = 9 data bits (SCCR1, M = 1)
Can be used for parity Can be used as an address marker (in “address-mark
variation”) telling a microprocessor when to sleep or wake up
LSB first
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UART: Parity Bit (optional) 1 Bit
Located at end of data bits (It is one of the data bits.) Even Parity
Parity bit = 1, if # of ones in the set is odd (you make total # even)
Odd Parity Some say more reliable (guarantees at least one data
transition) Parity bit = 1, if # of ones in the set is even (you make total
# odd) Note: Parity can be implemented with 8 Data Bits
when transmitting ASCII characters (since ASCII is represented with only 7 bits).
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UART: Stop Bit
1 bit (at end of message) Only used due to asynchronous nature
(synchronous Transmitters/Receivers don’t need start/stop bits)
It is the polarity of data-line’s idle state Idle state for HC11 = all 1’s stop bit = 1
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Ex: Packet Format
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Ex: Packet Format-ASCII character ‘H’ (without parity)
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Ex: Packet Format-ASCII character ‘H’ (with even parity and odd parity)
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Ex: Packet Format-ASCII character ‘l’ (with odd parity)
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Ex: Packet Format-ASCII character ‘EOT’ (with odd parity)
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UART: Noise
Problem: A premature ‘1’ or ‘0’ can make the HC11 Receiver think
that it’s receiving data before it really is or that it’s receiving incorrect data.
One Solution: HC11 takes 3 samples near the middle of each bit time
majority decision Another Solution:
Break Command (= all 0’s for >=1 character time, for HC11) Used to get attention of Receiver (i.e. change to default
rate)
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Ex: Full Transmission Format
(idle line) EOT ! o l l e H (idle line)
H = 0x48 = 0b1001000e = 0x65 = 0b1100101l = 0x6C = 0b1101100l = 0x6C = 0b1101100o = 0x6F = 0b1101111! = 0x21 = 0b0100001EOT = 0x04 = 0b0000100
Packet composition = Start Bit + 9 Data Bits [+ Parity Bit (odd parity scheme) as last Data Bit] + Stop Bit
Note: 9 Data Bit transmission was used (instead of 8) so that the receiver doesn’t store the parity bit in the SCDR register. (You can directly store SCDR [the ASCII values] to memory without having to take off the parity bit.)
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Advanced Features of HC11 UART
HC11 resynchronizes the Receiver’s bit clock on all 1-to-0 transitions (instead of just on startup)
HC11 takes 3 logic-samples near the middle of each bit time (majority rules)
HC11’s Receiver can enter a standby mode (“sleep mode”)
HC11 has a TC (Transmit Complete) Flag …in addition to the standard TDRE (Transmit Data Register Empty) Flag.
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References:
M68HC11ERG/AD Reference Guide (Rev. 2, 10/2003) M68HC11 Reference Manual (Rev. 4, 2001)
Section 9: p.317-366
Wikipedia.org: Asynchronous Serial Communication, UART, Parity (Used to get a fundamental understanding.)