![Page 1: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/1.jpg)
Readout for SiPMsPaul Rubinov
2/17/2009
![Page 2: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/2.jpg)
2
SiPMs readout for ?
► Define area of applicationThey are not Die eierlegende Woll-Milch-Sau
(approximate english translation: all-in-one device suitable for every purpose)
I will only address READOUT of device that aremoderate area (up to 5 x 5 mm )moderate pixel count ( up to 105 pixel )moderate speed (up to 1 ns resolution)
for HEP applications
R. Mirzoyan
![Page 3: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/3.jpg)
3
The Future
► I have seen the future of SiPM readout
Readout electronics will be integrated into the SiPM!because
SiPM is an inherently digital deviceWe ALWAYS convert the signal from the SiPM to digital So why do we have an analog step in between?!?
0pe
1pe
2pe
ADC
0pe
1pe
2pe
![Page 4: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/4.jpg)
4
The Future
► Ingredients required for integrated readout
1. SiPM is CMOS compatibleRMD makes SiPMs through Mosis
2. Will work for in HEP applicationsPixel architectures have demonstrated
readout of arrays like this
3. Cost effective(in volume)
![Page 5: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/5.jpg)
5
So why DIGITAL-ANALOG-DIGITAL?
►Because this requires an ASICThe people who make SiPMs do not know what we wantThe people who know what we want do not make SiPMs (yet)
Application Specific IC has to have a specific application
Because it gives us the most flexibility
![Page 6: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/6.jpg)
6
Back from the future
►Our current strategy is to maximize flexibilitywhich is the opposite of what we eventually want
![Page 7: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/7.jpg)
7
But remember the future...►The point of the AMP is to understand details
![Page 8: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/8.jpg)
8
Simulating SiPM
Parameterized models can be used to understand the details
![Page 9: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/9.jpg)
9
► It depends on Crp, but a reasonable guess is that about half the energy is in the spike and half in the “slow” part
► Studies of temperature dep can be used to understand
this is voltage
this is time integral of power
![Page 10: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/10.jpg)
10
Simulating SiPM
Parameterized models can be used to understand the details
![Page 11: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/11.jpg)
11
Simulation vs reality
![Page 12: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/12.jpg)
12
Can be used to look “inside”
![Page 13: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/13.jpg)
13
Can be used to look “inside”
So we see that the output signal is a slow recharge of the cell capacitance and a fast spike through the grid capacitance
![Page 14: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/14.jpg)
14
Next step(s): 4ch board► Still very generic, but now think infrastructure►Best available commercial components without
heroic efforts (~1ns resolution, ~400 pe range)► Integrated with SiPM specific features
(bias generator, current readback, temp sensor)►Optimized for medium ch count (dozen(s) SiPMs)► Flexible: using 50ohm input, generic daughter
board connection to support faster readout/more memory
► Large FPGA to allow DSP and TDC features
![Page 15: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/15.jpg)
15
Next step(s)
► Still very generic, but now think infrastructure
![Page 16: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/16.jpg)
16
► Still very generic, but now think infrastructure
CW bias generator
bias offset/ch
hi res current readback/ch
2 stages of diff amps
12bit, 250MSPS ADCs
largish FPGA
simple USB interface
daughter brd for faster interface
![Page 17: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/17.jpg)
17
► Still very generic, but now think infrastructure
CW bias generator
bias offset/ch
hi res current readback/ch
![Page 18: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/18.jpg)
18
Near future
►Move from more generic to more specific►Become tied to mechanics
(drop long 50ohm cables)
►Specific for:larger volume testing larger (specific) detector application
►Optimize for 100s of SiPMs
![Page 19: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/19.jpg)
19
Conclusion
► I think the way forward is clear
►To take full advantage of SiPMs,there must be an ASIC
►If we don’t do this, others will
It is that simple
![Page 20: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/20.jpg)
20
backup
![Page 21: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/21.jpg)
21IRST 1.8m with 120Gev Beam at 34V, I=1.1uA
![Page 22: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/22.jpg)
22
►NO Sr90 source ►MPPC-11-050C#37 at 71.1deg F operating
at 69.81 (recommended V is 70.02 at 25C)►Current reading is 0.044uA►1pe is about 13.25mV
![Page 23: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/23.jpg)
23
►Sr90 source – note different scale on Y!►MPPC-11-050C#37 at 71.1deg F operating
at 69.81 (recommended V is 70.02 at 25C)►Current reading is 0.160uA►1pe is about 13.25mV
![Page 24: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/24.jpg)
24
Low power
![Page 25: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/25.jpg)
25
Low power
![Page 26: Readout for SiPMs · hi res current readback/ch. 2 stages of diff amps. 12bit, 250MSPS ADCs. largish FPGA. simple USB interface. daughter brd for faster interface. 17](https://reader035.vdocuments.mx/reader035/viewer/2022081613/5fb9f77b6b56ab03fd08f683/html5/thumbnails/26.jpg)
26
ProposalThis trace is the simulation of 1pe from an SiPM similar to IRST or MPPC400 at a gain of about 350k
It gives about 5mV output with a decay time of ~1us
Power consumption <10mW