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Programmable Logic Devices
Roth Text: Chapter 3 (sections 3.1-3.3) Nelson Text: Chapter 5 (combinational)
Chapter 11 (sequential)
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Programmable logic taxonomy
LabDevice
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History of Programmable Logic Programmable Logic Arrays ~ 1970
Incorporated in VLSI devices Can implement any set of SOP logic equations
Outputs can share common product terms Programmable Logic Devices ~ 1980
MMI Programmable Array Logic (PAL) 16L8 – combinational logic only
8 outputs with 7 programmable PTs of 16 input variables 16R8 – sequential logic only
8 registered outputs with 8 programmable PTs of 16 input variables Lattice 16V8
8 outputs with 8 programmable PTs of 16 input variables Each output programmable to use or bypass flip-flop
Complex PLDs – arrays of PLDs with routing network Field Programmable Gate Arrays ~ 1985
Xilinx Logic Cell Array (LCA) CPLD & FPGA architectures became similar ~ 2000
Incorporation of RAMs and other specialized cores Programmable system-on-chipPLDs 4
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Programming Technologies PLAs were mask programmable PALs used fuses for programming Early PLDs & CPLDs used floating gate
technology Erasable Programmable Read Only Memory (EPROM)
Ultra-violet erasable (UVEPROM) Electrically erasable (EEPROM) Flash memory came later and was used for CPLDs
FPGAs used RAM for programming Later trends
Fuses were replaced with anti-fuses Better reliability
Large CPLDs went to RAM-based programmingPLDs 5
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Programming Technologies PLAs were mask programmable PALs used fuses for programming Early PLDs & CPLDs used floating gate
technology Erasable Programmable Read Only Memory (EPROM)
Ultra-violet erasable (UVEPROM) Electrically erasable (EEPROM) Flash memory came later and was used for CPLDs
FPGAs used RAM for programming Later trends
Fuses were replaced with anti-fuses Better reliability
Large CPLDs went to RAM-based programmingPLDs 6
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Programming Technologies Floating gate technologies
Non-volatile but re-usable UV EPROM, EEPROM, and flash memory
In-System Programmable (ISP) EEPROM and flash memory
In-System Re-programmable (ISR) Flash memory
EPROM transistor – Programming voltage forces charge into floating gate.(trapped until given energy to escape)[Altera EPLDs, Xilinx EPLDs]
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Programming Technologies Fuse/anti-fuse
Non-volatile but not re-usable One Time Programmable (OTP)
Antifuse - Open until programming current melts dielectric (one time only) [Actel PLICE©]
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Programming Technologies RAM
Volatile – must configure after power-up In-System Re-programmable (ISR) Run-Time Reconfiguration (RTR)
dynamic reconfiguration while system is operating
SRAM cell
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Logic functions in read-only memory (ROM)
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ROM on next slide
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Programmable logic array structure
Each one “product”of the inputs
Each one “sum”of the products
Implement sum of products logic expressions
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NOR function in programmable logic
Xi = 0 turns transistor OFF (transistor = open circuit)Xi = 1 turns transistor ON (transistor shorts Z to ground/0)+V pulls Z up to 1 if not shorted to ground
Truth Table:X1 X2 Z0 0 1 - both transistors OFF/Z pulled up to +V0 1 0 - transistor 2 ON/shorts Z to ground1 0 0 - transistor 1 ON/shorts Z to ground1 1 0 - both transistors ON/short Z to ground
Manipulate sum of products form to use NOR-NOR structuresPLDs 16
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PLA implements SOP forms
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products sum EquivalentAND-OR form
𝐹𝐹0 = �̅�𝐴 �𝐵𝐵 + 𝐴𝐴 ̅𝐶𝐶
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Inputs and complementstypically provided in PLA
Compact representation of product
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PLA with 3 inputs/5 products/4 sums
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Compact representation of previous PLA circuit
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Minimize multiple functions concurrently(minimize # product terms)
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Sequential circuit implementation
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BCD to Excess-3 Converter
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Programmable Array Logic (PAL)
AND array programmable
OR array fixed
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Full adder with a PAL
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PALs16L8 – combinational logic 10 to 16 inputs, each with
true and complement signal
2 to 8 outputs, each with 7 product terms can AND
any of up to 16 inputs or their complements
Tri-state control product term for inverting output buffer When output in tri-
state, I/O pin can be used as input High impedance
output with no signal driven
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Sequential PAL
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Sequential circuit with a PAL
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PALs16R8 – sequential logic 8 inputs, each with true &
complement 8 outputs, each with
D flip-flop With feedback for FSMs
8 product terms that can AND any of: 8 inputs or their
complements 8 feedbacks or their
complements from D flip-flops
One clock for all FFs One tri-state control for all
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PLD Basic Structure Programmable product terms (AND plane)
AND gates can connect to any input/FF bit or bit-bar Fixed OR plane determine maximum # PTs Programmable macrocell
XOR gate selects SOP or POS for fewer PTs FF for sequential logic or bypass for combinational logic Feedback current state into array for FSM design
In
Inputs and Current State from FFs (Bit & Bit-Bar)
Out
CBCB
In•Qbar
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PLDs22V10 replaced all PALs Combinational and/or sequential
logic Macrocell program bits C0, C1
Up to 22 inputs w/complement Up to 10 outputs, each with
Macrocell 8-16 product terms Tri-state control product term
Global preset & clear PTs clock
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22V10: “V” => versatile outputs
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PLDs
of 22V10
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CPLD implementation of a Mealy machine
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Complex PLDs (CPLDs) An array of PLDs
Global routing resources for connections PLDs to other PLDs PLDs to/from I/O pins
Example: Cypress 39K Each Logic Block (LB)
similar to a 22V10 Each cluster of 8 LBs
has two 8K RAMs & one 4K dual-port RAM/FIFO Programmable
Interconnect Modules (PIMs) provide interconnections
Array of up to 24 clusters with global routing
I/O Block
4096 bitRAM
Dual-PortFIFO
LB
PIM
8192 bitRAM
LBLBLB
LB
8192 bitRAM
LBLBLB
I/O B
lock
I/O B
lock
I/O Block
4096 bitRAM
Dual-PortFIFO
LB
PIM
8192 bitRAM
LBLBLB
LB
8192 bitRAM
LBLBLB
I/O Block
4096 bitRAM
Dual-PortFIFO
LB
PIM
8192 bitRAM
LBLBLB
LB
8192 bitRAM
LBLBLB
4096 bitRAM
Dual-PortFIFO
LB
PIM
8192 bitRAM
LBLBLB
LB
8192 bitRAM
LBLBLB
I/O B
lock
I/O B
lock
4096 bitRAM
Dual-PortFIFO
LB
PIM
8192 bitRAM
LBLBLB
LB
8192 bitRAM
LBLBLB
4096 bitRAM
Dual-PortFIFO
LB
PIM
8192 bitRAM
LBLBLB
LB
8192 bitRAM
LBLBLB
I/O Block I/O Block I/O Block
GCLK[3:0]
GCLK[3:0]
GCLK[3:0]
CNTL[3:0]4
4
8
PLLs &Clock Mux
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Altera MAX architecture(PAL-based logic modules)
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