Download - Powerpoint Templates Page 1 Dr. Wissam Hasan Mahdi Alagele e-mail:[email protected] وزارة التعليم
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Dr. Wissam Hasan Mahdi Alagele
e-mail:[email protected]
http://edu-clg.kufauniv.com/staff/Mr.Wesam
العلمي والبحث العالي التعليم وزارةالكوفة الحاسوب- – جامعة علوم قسم التربية كلية
Chapter 3Decoder and Encoder
Digital Logic Design III
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Decoder definition
• Decoding is the conversion of an n-bit input code to an m-bit output code with n ≤ m ≤ 2n, such that each valid code work produces a unique output code.
• Decoding is performed by a logic circuit called a decoder.
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Binary Decoder
• Black box with n input lines and 2n output lines• Only one output is a 1 for any given input
BinaryDecoder
ninputs 2n outputs
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Decoders A decoder has
N inputs 2N outputs
A decoder selects one of 2N outputs by decoding the binary value on the N inputs.
The decoder generates all of the minterms of the N input variables.
Exactly one output will be active for each combination of the inputs.
What does “active” mean?
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Decoders• Extract “Information” from the code• Binary Decoder
– Example: 2-bit Binary Number
BinaryDecoder
x1
x0
Only one lamp will turn on
0
0
1000
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n-to-m-line decoders
• Circuit has n inputs and m outputs and m ≤ 2n
• Start with n=1 and m=2• This a 1-to-2 Line decoder – exactly one of the output
lines will be active.
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Decoders
I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Bin
ary
Dec
oder I1
I0
y3
y2
y1
y0
I1I0
Y3
Y2
Y1
Y0
013 IIY 012 IIY
011 IIY 010 IIY
A decoder when n=2 and m=4A 2-to-4 line decoderNote that only one output is ever active
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Truth Table, 3-to-8 Decoder
• Notice they are minterms
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Decoders• 3-to-8 Line Decoder
Bin
ary
Dec
oder
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
I2
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
I1
012 III
012 III
012 III
012 III
012 III
012 III
012 III
012 III
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Enable
• Enable is a common input to logic functions• See it in memories and today’s logic blocks
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Decoders• “Enable” Control
Bin
ary
Dec
oder I1
I0
E
Y3
Y2
Y1
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
EI0
Y3
Y2
Y1
Y0
I1
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Decoders• Expansion
I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0
I2 I1 I0
Bin
ary
Dec
oder I0
I1
E
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Bin
ary
Dec
oder I0
I1
E
Y3
Y2
Y1
Y0
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Decoders• Active-High / Active-Low
I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
I1 I0 Y3 Y2 Y1 Y0
0 0 1 1 1 0
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 1 1 1
Bin
ary
Dec
oder I1
I0
Y3
Y2
Y1
Y0
I1I0
Y3
Y2
Y1
Y0
Bin
ary
Dec
oder I1
I0
Y3
Y2
Y1
Y0
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Implementation Using Decoders• Each output is a minterm• All minterms are produced• Sum the required minterms
Example: Full Adder
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
BinaryDecoder
xyz
S C
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Implementation Using Decoders
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
BinaryDecoder
xyz
S C
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
BinaryDecoder
xyz
S C
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Encoders An encoder has
2N inputs N outputs
An encoder outputs the binary value of the selected (or active) input.
An encoder performs the inverse operation of a decoder.
Issues What if more than one input is active? What if no inputs are active?
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Encoders• Put “Information” into code• Binary Encoder
– Example: 4-to-2 Binary Encoder
x3 x2 x1 y1 y0
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
1 0 0 1 1
BinaryEncoder
y1
y0
x1
x2
x3
Only one switch should be activated at a time
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Encoders• Octal-to-Binary Encoder (8-to-3)
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 10 0 0 0 0 1 0 0 0 1 00 0 0 0 1 0 0 0 0 1 10 0 0 1 0 0 0 0 1 0 00 0 1 0 0 0 0 0 1 0 10 1 0 0 0 0 0 0 1 1 01 0 0 0 0 0 0 0 1 1 1
Bin
ary
En
cod
er Y2
Y1
Y0
I7
I6
I5
I4
I3
I2
I1
I0
13570
23671
45672
IIIIY
IIIIY
IIIIY
I7I6I5I4I3I2I1I0
Y2
Y1
Y0
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Encoder / Decoder Pairs
Y2
Y1
Y0
I7
I6
I5
I4
I3
I2
I1
I0
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
BinaryEncoder
BinaryDecoder
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Multiplexers
MUX Y
I0
I1
I2
I3 S1 S0
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
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Multiplexers• 2-to-1 MUX
• 4-to-1 MUX
MUX YI0
I1 S I1
I0
S
Y
MUX Y
I0
I1
I2
I3 S1 S0
I1
I0
S1
YI2
I3
S0
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Multiplexers• Quad 2-to-1 MUX
MUX YI0
I1 S
MUX YI0
I1 S
MUX YI0
I1 S
MUX YI0
I1 S
x3
x2
x1
x0
y3
y2
y1
y0
S
Y3
Y2
Y1
Y0
S E
A3
A2
A1
A0
B3
B2
B1
B0MUX
A3
A2
A1
A0
S E
Y3
Y2
Y1
Y0
B3
B2
B1
B0
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Multiplexers• Quad 2-to-1 MUX
Y3
Y2
Y1
Y0
S E
A3
A2
A1
A0
B3
B2
B1
B0
MUX
A3
A2
A1
A0
S E
Y3
Y2
Y1
Y0
B3
B2
B1
B0
Extra Buffers
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Implementation Using Multiplexers• Example
F(x, y) = ∑(0, 1, 3)
MUX Y
I0
I1
I2
I3 S1 S0
x y F
0 0 1
0 1 1
1 0 0
1 1 1x y
F
1101
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Implementation Using Multiplexers• Example
F(x, y, z) = ∑(1, 2, 6, 7)
x y z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
MUX Y
I0
I1
I2
I3 I4
I5
I6
I7S2 S1 S0
x y z
01100011
F
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Implementation Using Multiplexers• Example
F(x, y, z) = ∑(1, 2, 6, 7)
MUX Y
I0
I1
I2
I3 S1 S0
x y z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
x y
FF = zz
F = z
z
F = 0
0
F = 1
1
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Implementation Using Multiplexers• Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
MUX Y
I0
I1
I2
I3 I4
I5
I6
I7S2 S1 S0
A B C D F0 0 0 0 00 0 0 1 10 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1 A B C
F
F = DD
F = DD
F = D
D
F = 0
0
F = 0
F = D
F = 1
F = 1
0
D
1
1
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Multiplexer Expansion• 8-to-1 MUX using Dual 4-to-1 MUX
Y
I0
I1
I2
I3
I4
I5
I6
I7
S2 S1 S0
MUX Y
I0
I1
I2
I3 S1 S0
MUX Y
I0
I1
I2
I3 S1 S0
MUX YI0
I1 S
0 01
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DeMultiplexers
DeMUXI
Y3
Y2
Y1
Y0S1 S0
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
I
Y3
Y2
Y1
Y0
S0S1
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Multiplexer / DeMultiplexer Pairs
Y
I7
I6
I5
I4
I3
I2
I1
I0
I
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
MUX DeMUX
S2 S1 S0 S2 S1 S0
x2 x1 x0 y2 y1 y0
Synchronize
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DeMultiplexers / Decoders
Bin
ary
Dec
oder I1
I0
E
Y3
Y2
Y1
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
DeMUXI
Y3
Y2
Y1
Y0S1 S0
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
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Three-State Gates• Tri-State Buffer
• Tri-State Inverter A Y
C
C A Y
0 x Hi-Z
1 0 0
1 1 1
A Y
C
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Three-State Gates
A
YC
B
D
C D Y
0 0 Hi-Z
0 1 B
1 0 A
1 1 ?
Not Allowed
Y=
A
C
B
A if C = 1B if C = 0
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Three-State Gates
I0
Y
E
S1
I1
I2
I3
Bin
ary
Dec
oder I1
I0
E
Y3
Y2
Y1
Y0
S0