Power-Aware and BIST-Aware NoC Reuse on the Testing of
Core-based Systems
Érika Cota Luigi Carro
Flávio Wagner Marcelo Lubaszewski
UFRGS
Porto Alegre, Brazil
b a c k n e x t h o m e
Context
SoC
core core core
corecorecore
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Reuse Model
tester
SoC
core core core
corecorecore
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Reuse Model
tester
SoC
core core core
corecorecore
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Reuse Model
tester
SoC
core core core
corecorecore
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Revisão dos principais objetivose fatores de sucesso
Improve the reuse the on-chip network as test access mechanism
minimal area overhead zero pin overhead feasible test time
Power consumption is an issue?
Optimal set of BISTed cores?
Goal
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Revisão dos principais objetivose fatores de sucesso
NoC-based Test
Power consumption calculation
Modified scheduling
Considering BISTed cores
Experimental Results
Final Remarks
Outline
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Access Paths Within the NoC
CUT 1
CUT 2
input
input
output
output
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Access Paths Within the NoC
CUT
CUTCUT 2
CUT 1
input
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Access Paths Within the NoC
CUT
CUTCUT 2
CUT 1
input
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Access Paths Within the NoC
CUT
CUTCUT 2
CUT 1
output
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Access Paths Within the NoC
CUT
CUTCUT 2
CUT 1
output
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Access Paths Within the NoC
CUT
CUTCUT 2
CUT 1input
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Access Paths Within the NoC
CUT
CUTCUT 2
CUT 1
input
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Access Paths Within the NoC
CUT
CUTCUT 2
CUT 1
output
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Access Paths Within the NoC
CUT
CUTCUT 2
CUT 1
output
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Parallelism Within the NoC
CUT 1
CUT 2
input
output
input
output
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Pipeline Within the NoC
CUT 1
CUT 2
CUT 3
input
output
output
input
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Pipeline Within the NoC
CUT 1
CUT 2
CUT 3
input
output
input
output
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Pipeline Within the NoC
CUT 1
CUT 2
CUT 3
input
output
output
input
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Pipeline Within the NoC
CUT 1
CUT 2
CUT 3
input
output
BOTTLENECKS!
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Packets Scheduling
CUT 1
CUT 2
CUT 3
input
output
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Packets Scheduling
CUT 1
CUT 2
CUT 3
input
output
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Packets Scheduling
CUT 1
CUT 2
CUT 3
input
output
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Packets Scheduling
CUT 1
CUT 2
CUT 3
input
output
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Packets Scheduling
CUT 1
CUT 2
CUT 3
input
output
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Reuse Algorithm
Define test packets
Define access paths for each core
Select a packet
Find available access path
Schedule packet
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Power Consumption Calculation
Router
Core 2
Router
Core 3
Router
Core 4
Router
Core 5
Router
Core 6
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
Router
Core 1
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Power Consumption Calculation
Router
Core 2
Router
Core 3
Router
Core 4
Router
Core 5
Router
Core 6
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
Router
Core 1
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Power Consumption Calculation
Router
Core 2
Router
Core 3
Router
Core 4
Router
Core 5
Router
Core 6
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
Router
Core 1• F(#ffs, #gates, switching rate)• per cycle (any frequency)• per packet
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Power Consumption Calculation
Router
Core 2
Router
Core 3
Router
Core 4
Router
Core 5
Router
Core 6
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
Router
Core 1• F(length,width,switching rate)• per cycle (any frequency)
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Power Consumption Calculation
Router
Core 2
Router
Core 3
Router
Core 4
Router
Core 5
Router
Core 6
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
wrapp
er
Router
Core 1
• F(#ffs, #gates, switching rate)• per cycle (any frequency)• per pattern
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Power Consumption of One Packet
CUT
CUT
CUT 1
input
4*PW(router) + 3*PW(channel) + PW(CUT+wrapper)
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Power-Aware Scheduling
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Power-Aware Scheduling
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Power-Aware Scheduling
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Experimental Setup
SOCIN Network– under development at UFRGS– Grid topology– 32-bit channels– deterministic routing (XY)
ITC’02 SoC Test Benchmarks– d695, g1023– Placement for synthetic applications
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Experimental Results - d695
Cores consumption >> wrapper consumptionT
est
time
Power Limit
0
10000
20000
30000
40000
50000
nolimit
50% 40% 30% 20% 10%
1 in / 1out
2 in / 2 out
3 in / 3 out
4 in / 4 out
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Experimental Results - g1023
Cores consumption >> wrapper consumption
Inputs/Outputs
No powerLimit
50% 30% 20% 10%
1/1 52145 52145(0%)
52296(0.29%)
51853 33521
2/2 31898 31547(-1.1%)
33032(3.56%)
41016 67962
3/3 22648 24869(9.8%)
25873(14.2%)
37757 64557
4/4 18851 19776(4.9%)
31488(67%)
37871 66088
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Experimental Results - d695
Cores consumption wrapper consumptionT
est
time
Power Limit
01000020000300004000050000600007000080000
nolimit
50% 40% 30% 20% 10%
1 in / 1out
2 in / 2 out
3 in / 3 out
4 in / 4 out
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Experimental Results - g1023
Cores consumption wrapper consumption
Inputs/Outputs
No powerLimit
50% 30% 20% 10%
1/1 52145 835 - - -
2/2 31898 34355 61 61 -
3/3 22648 38598 102 61 -
4/4 18851 38633 158 61 -
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BIST-Aware Scheduling
Each core has a BISTed version– 30% more area– 50% more power consumption– 2x the number of test vectors
All cores BISTed– system test time = largest test time among
cores– power consumption may be na issue
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BIST-Aware Scheduling
1) All cores BISTed
– maximum parallelization
– minimum test time?
2) Define test scheduling considering power constraints
3) Replace the core with largest test time by its external tested version
4) Repeat 2 and 3 until test time increases
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Experimental Results - p22810
No power constraints
BISTed Cores
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Experimental Results - p22810
No power constraints
BISTed Cores
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Experimental Results - p22810
No power constraints
BISTed Cores
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Experimental Results - p22810
Multiple BIST model
BISTed Cores
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Final Remarks
Alternative TAM for NoC-based SoCs
good trade-off test time x area X pin overhead even under power constraints (ETW’03)
Selection of the optimal set of BISTed cores for test time minimization (TRP’03)
Further selection of the best BIST method for the cores in the system