Plasma Dicing of Si Wafers with Panasonic APX300
James Weber
Panasonic Industry Europe GmbH
Agenda
1.Features of Plasma dicing process
2.Panasonic process strategy
3.Plasma dicing demonstration center
1. Features of Plasma Dicing Technology
Blade dicing Plasma dicing
Gas Etching
✓ Damage Free
Mechanical
Introduction of new process “Plasma dicing”
Chipping
✓ Damage
Blade Dicing Laser Dicing Plasma Dicing
Figure
Dicing Process Mechanical process Laser + expand process Plasma etching process
Dicing Speed 10~50mm/s 300mm/sDepend on
wafer thickness(Si: >20μm/min)
Chip StrengthLower
(Chipping・Crack)Lower
(Crack・Laser damage)Higher
(Stress free)
Low-kApplicability
Unsuited (delamination,Wafer usage process)
Suited Suited
Comparison of Dicing Processes
TEM images of chip side wall
Blade Dicing Plasma Dicing
Nondamage
Damage Free Process
0.5μm
Blade Dicing Plasma Dicing
60μm
Increasenumberof chips
Number of chips in wafer
Blade Plasma
20µm
116,000
Dicing width
Number of chips
60µm
97,000
Yield
improvement
+20%
(8inch wafer,□0.5mm)
Dicing Width of Plasma Dicing
Hexagonal chipRound chip
Shift ofchip placement
Variantchip shape
Variant Chip Shape by Plasma Dicing
Etching Time 5min
Experiment conditions
•Etching time: 5 min
•Dicing width: 15 μm
•Si dummy wafer
Etching rate >25μm/min(30μm/min is achieved in case of thin wafer)
High Etching Rate
Blade dicing Plasma dicing
Optical
TEM
Front side(Device surface)
Backside
Backside Backside
Front side(Device surface)
Backside
Chipping ChippingFree
ChippingFree
Chipping
TEM
DamageLayer
Damagefree
Damage free process
Plasma dicing can prevent chip damage.
2536 1280
941 25361329 2534
17762054
1415 2482 1162831 1427 2016 1319 7121598 916
9101069
1529 6701867 1102
1939 1432
Higher bending strength with narrow distribution
Mapping data
Plasma Dicing
Blade Dicing
[Note] Si wafer size : 8 inchchip size : 5x15mmThickness : 150um
Chip strength test
3 point bending
Bending strength(MPa)
In
teg
rate
d f
req
uen
cy(
ー)
3 point bending test result
Breaking mode of Si chip
Crack/Chipping
Blade dicing(cleavage mode)
Cleavage separation
Before
After
broken-out section
Plasma dicing(Crushing mode)
Material crush out
Damage less
トレイ- -
磁界
電子
Low inductance coil → High efficiency・High density plasma・Wide range of discharge window・Uniform large scale plasma
Multi
Single
Chamber configuration
I-sa
t curr
ent
Branch number
Wafer Position
Patented
ダイシングリングダイシングリング
Chamber vessel
Quartz Plate
Wafer
Bias
Dicing ring
Electric
Ion
ICP coil
Magneticfield
Matching unit
RF
RF
Plasma source ~Multi Spiral ICP(MSC-ICP)~
Controlled tape temperature enables high etch rate
◆ Wafer with dicing tapeStandard dry etcher gives tape melt due to heat from plasma
(Heat resisting property ~100℃)
Tape melt
plasma
RingWafer
Coolingwater
ESC
Original cover
Original ESC
plasma
Cooling water
Prevent heat damage
Standard Dry Etcher Panasonic Plasma Dicer◆ Panasonic’s solution① Original ESC
improves cooling efficiency between wafer/tape/chuck
② Original coverprevents exposure of tape from plasma
How to etch a wafer with tape by plasma?
Equipment Process
〇 Panasonic has not only many equipment patents, but also process patents.〇 Examples of Panasonic’s fundamental patents
USP8,513,097 Fundamental equipment patent for wafer with dicing frame USP6,897,128 Process patent for process flow of plasma dicingUSP7,964,449 Process patent for Laser scribe + Plasma dicing
Patent Comparison between Panasonic and others
PlasmaSource
Processflow
8(6)
1
14(9)
2
5(4)
2
5(2)
11
16(9)
25(7)
Others
Chamber Transfer Quality Mask
US⇒
JP⇒
Patent Strategy for Plasma Dicing
2. Panasonic Process Strategy
Brittle
Thin Thin Brittle
Source) http://pr.fujitsu.com/jp/news/2003/06/25-2.html
Source) http://www.aset.or.jp/kenkyu/kenkyu_seika_comp_7.html
Source) http://panasonic-denko.co.jp/ac/j/tech/pimites/explan_tech/what_tech_001/index.jsp
Source) http://www.hitachi.co.jp/inspire/hakken/blue/04_mu_chip.html
Source) http://www.aset.or.jp/kenkyu/kenkyu_seika_comp_7.html
Dimensional/mechanical trend in IC chip
Chip goes “Thin・Brittle・Small”
SmallChip
Wafer
3D/TSV
Image Sensor
MEMS
Memory
Low-kRF-ID
Plasma dicing target area
Blade Dicing
Laser Dicing
Plasma Dicing
Thin and Small chips are target area of plasma dicing
Thick
Middle
Thin
Thic
kness
(μm
)
1 3 7
Chip Size(mm□)
Memory(Chipping)
DiscreetChip
・RFID
(Number)
Logic
Sensor・MEMS
(Number)(Particle)
Commodity IC etc.
700
100
200
300
400
Driver IC etc.
Plasma dicing target area
Point
Benefits of Plasma dicingTarget
ApplicationBlade issue Benefit by plasma
IoTSmall chip
・RF-ID tag・Chip component・MEMS etc..
Wider dicing lane
(W 60μm)
Narrower lane(W 20μm) More chips from a wafer
Longer process time in smaller
dies
Shorter process time
lower COO
Image Sensor
Particle from blading, less yield
Particle freeimprove yield
Memory
Chipping/die breakage
due to damage
Damage free chip obtained
new value for end user
Blade Plasma
Mechanicalbase
↓
Gas base
Damage No damage
Blade Plasma
Source)Panasonic HP
0.2mm
0.1mm
60μm 20μm
Memoryー
CPU
25μm
Line-by-line Whole wafer
Process scenarios
Appli-cation
Chipsize
Wafer StructureProcess
Mask formation Dicing
IoTSmallChip Small
(~3mm)
Photolithography Plasma
Image sensor
Large(3mm~)
Mask tapeOr coating
Laser Plasma
Memory/Logic
Coat/Expo. Dicing
DicingCut mask &Metal layer
Lamination
Liquid
Develop.
Two processes cover target applications
Si
Mask
Si
Metal/Low-k
MaskLaserPatterning
Si
Plasma Dicing
Plasma Dicing
Si
ターゲットカテゴリ
チップサイズ
ウエハーの断面構造
工法1:フォトリソ+プラズマ
ウエハー薄化 フォトリソによるマスクパターン形成 ダイシング
小チップ• チップ部品• RF-ID• MEMS 等
小さい
保護テープ貼付
裏面研削レジスト塗布
露光 現像 ベークダイシングシート貼付
プラズマダイシング
イメージセンサー*
大きい
工法2:レーザー+プラズマ
ウエハー薄化 レーザー加工によるマスクパターン形成 ダイシング
保護テープ貼付
裏面研削ダイシングシート貼付
(保護テープの一部を残す)レーザースクライブ プラズマダイシング
メモリー
ウエハー反転
マスク
基材接着層
ウエハ
0.2mm
0.1mm
メモリー
CPU
50μm
* 出所) パナソニックHP プレスリリース
Si
マスク
Si
メタル配線
マスクレーザーパターンニング
Si
プラズマダイシング
プラズマダイシング
Si
Alliance between Panasonic & partners[Coater]
EVG[Developer]
SUSS Microtec
[Mask tape]Furukawa
[Gas related]Taiyo-Nippon Sanso
[Laser]Accretech
2-1 Photolitho+ Plasma Dicing
BG
Damage layer
Stress Relief
Spin Coat
Photo Litho
Plasma dicing ( Si etching )
SF6
O2 Plasma
BG Tape
725µm
Die pick up
BG tape De-lamination
Plasma dicing ( Ashing )
Dicing tape lamination
Photolitho + Plasma Dicing from device surface
BG
Damage layer
Stress Relief
Spin Coat
Photo Litho
Plasma dicing ( Si etching )
BG Tape
SF6
O2 Plasma
TEG
BG Tape
725µm
Die pick up
BG tape De-lamination
Plasma dicing ( Ashing )
Dicing tape lamination
Photolitho + Plasma Dicing from back surface
2-2 Laser Patterning + Plasma Dicing
Process scenarios
Appli-cation
Chipsize
Wafer StructureProcess Flow
Mask Patterning Dicing
IoTSmallChip Small
(< 2mm)
Photolithography Plasma
Image sensor
Large(> 3mm)
Coating Laser Plasma
Memory
Coat/Expo. Dicing
DicingPatterning
Liquid
Develop.
Two main processes cover our target applications
Si
Mask
Si
Metal/Low-k
MaskLaserPatterning
Si
Plasma Dicing
Plasma Dicing
Si
Two mask methods of plasma dicing
①BG tapedelamination
Furukawa
BG mask tape
(special tape)
BG mask tape(Furukawa)
Water-solublemask
②Coating ④Plasma dicing③laser grove ⑤Removing
Non(Low cost)
Remainedmask film
Base filmof BG tape
Ashing
Water rinseSpin or Spray
(water-soluble)
BG mask tape and water-soluble mask are available
Two mask methods of plasma dicing
①BG tapedelamination
Furukawa
BG mask tape
(special tape)
BG mask tape(Furukawa)
Water-solublemask
②Coating ④Plasma dicing③laser grove ⑤Removing
Non(Low cost)
Remainedmask film
Base filmof BG tape
Ashing
Water rinseSpin or Spray
(water-soluble)
BG mask tape and water-soluble mask are available
Key Technology of Laser + Plasma Process
Laser Patterning Plasma Cleaning Panasonic Process Patent
Plasma dicing can etch not only thin Si wafer but also DAF tape
Center
Edge
DAF
Si
DAF
Si
DAF
Si
DAF (20um)
Si (50um)
Thin Wafer Dicing by Laser + Plasma process
Chip Strength of Laser + Plasma Process
Chip strength of laser + plasma process is same as
one of photo process Blade
Photolith+ plasma
FurukawaBG mask+ plasma
Typical structure of wafer with bumps
Si 725/775μm 200~25μm etc..
Solder bump / Cu-pillar + solder cap
30~250μmH
RDL
SiO2
Dicing street
Dicing street
Many semiconductor wafers have some bumps/pads
How to handle such bumps in plasma dicing process?
50~100μmW
Pre-test sample structure / target
Φ8” Si-sub
Mask (PR)-Thick: 10μmOpen Width-Laser: 30μm-Litho: 10μm
Original dicing street : ~100μm
SiO
Solder ballΦ250μm
5x5mm chip
Covers whole ball
initial After coating
Solder ballΦ250μm
Conformal coating achieved !
[key 1] ~Conformal coating of solder ball~
These photographs are courtesy of EVGroup.
Open by Aligner
100μm
SiO
Solder ballΦ250μm
5x5mm chip
Covers whole ballGap
>200μm
10μm
Alignment & Exposure with a big gap executed !
[key 2a] ~Street opening by Lithography~
[key 2b] ~Street opening by Laser~
30μm
Laser Patterning successfully done !
3. Plasma Dicing Demonstration Center
What makes difficult when exploring plasma
Rapid demonstration with different products
Total solution incl. material and equipment
Secure highly confidential wafer when hand over many different venders
Preparing demonstration site is essential !
◆Requests from customer
Vendor C
BG tape BGPhotolithography
Vendor A
Laser
Vendor D
Plasma dicer
Panasonic (Japan)
Vendor B
“Plasma dicing demonstration center”
Founded Oct. 12nd, 2016
Location Osaka, Japan
Floor Space 230m²
Spec(Clean room)
-Class : 1,000(φ0.5μm)
-Temperature : 23±3℃-Relative & humidity : 50±20%
Plasma dicer APX300 X 2 machines
Wafer Φ300mm・φ200mm min 25umt
Process
Polish grinder Thinning wafer. Min. 25μm thickness(coming early 2017)
Lithography Open mask street by photolithography technique. Min. few μm width
Laser patterning Open metal/low-k layer. Min 15μm width
Plasma dicer Full cut bulk-Si layer by deep-Si etching. High speed > 25μm/min.
Measurement Surface profile, thickness and optical analysis
“Plasma dicing demonstration center”
● Equipment line-up(φ8 & φ12inch applicable)
Plasma LithoBG/Tape
MeasureLaser
DeveloperLaser patterning SEM Profiler thickness Coater
Polish grinder
Vacuum laminator Φ8”Plasma dicer Φ12”Plasma dicer Bake plateHMDS
Vapor primerBG tape laminator
Mask aligner
Class 1000cleanroom
Yellowroom
Equipment
Conclusion
Panasonic provides and support customerby “one-stop solution” for plasma dicing
ProcessMaterial
Litho
Tape
Laminator
Measurement
BG
Laser
Plasmadicer
Thank you for your attention.
Please contact James Weber for more information.
Visit us at the Panasonic Booth in Hall A4, Nr 474.