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May 9, 2005
PIPE DREAM
Out-of-Order Speculative CPU
Karthik Balakrishnan and Michal Karczmarek
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The Plan
Out-of-orderSpeculativePhysical register fileSingle-issueNon-blocking, in-order memory unitBranch predictionPrecise exceptions
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The Basic Design: Data Flow
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The Basic Design: Branch Taken
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Register Rename Unit
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Re-order Buffer
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Design Exploration: Data Flow
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Design Exploration:- Branch Predictor
Use a standard 2-bit predictor
No global history (even though it was originally planned)
Carry a “branchTaken” bit to allow Execute to check if prediction was correct
2-bit Branch Predictor
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Design Exploration:- Branch Predictor
PCBranch History Table
WNT
WT
WT
SNTtake/don’t take
Hash on bottom bits of instruction PC
Initialize to WT
Predict all branch instructions and force take J and JAL
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Design Exploration:- Out of Order Scheduling
Find which instructions are ready to goDispatch memory operations in order (speculatively)Send stores to memory when retiredUse barrier instructions for COP0
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Design Exploration:- Out of Order Scheduling
Schedule in-order and out-of-order instructions separately
Be careful about the wrap-around
ROB Entries
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Place and RouteROB IPCF REGS
RENAME MMUEXEC
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Results
3616345170491744919610013110212796123vvadd
612756647368861725498767510113997909qsort
speculative memory unit
fast predict
fast mispredictbp/oooooobpbasic
Final clock period was 9.803nsFinal area 458569.6 um2
qsort retires 24249 instructions (ipc=0.4)vvadd retires 18026 instructions (ipc=0.5)vvadd loop: 10 instructions, 16 cyclesusing our own harness, still adapting to Chris’sNumber of cycles to complete benchmark:
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Interesting ProblemsBluespec infinite compile times: 12-entry ROB compilesin 2 mins; 14-entry ROB hangs forever
RWires are necessary but EVIL
Branch predict: Bug with predicting JR and JALR, noting it’s been “taken” but going to the wrong target!
Lots of bug in decode and execute: all fixed once we passed self_test, test_spim and test_all (renaming/out-of-order didn’t introduce execution bugs)
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Special Thanks To:
6884-bluespecChris
The End
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Slowest Data PathretireInstrQ retireIPCQ