Optimization of Wafer Level Test Hardware using Signal Integrity
Simulation
Jason MroczkowskiRyan Satrom
June 7-10, 2009San Diego, CA
June 7 to 10, 2009June 7 to 10, 2009 IEEE SW Test WorkshopIEEE SW Test Workshop 22
• Industry Drivers• Wafer Scale Test Interface Simulation• Simulation Techniques• Capturing Interfaces• Full Test Interface Simulation Example
– Components that most impact performance– Optimization of interfaces– Full system results
Agenda
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Wafer Scale Test - Industry Drivers
• Industry Expectations– Short lead-times– Low cost - varies with complexity– High quality - First Pass
Success!• Challenges
– DUT complexity - faster, smaller, integrated
– Test hardware complexity - fine pitch, low inductance, matched impedance
Don’t let this happen to you
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Lowering the Cost of Test• Eliminate Guesswork Through
Signal Integrity Simulation• Ensure performance prior to fabrication• Eliminate re-spins and time consuming lab
analysis
• Simulate All Structures in the Path from the Tester to the DUT
Tester Probe Card IC Device (DUT)
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Test Interface Simulation• Focus on Critical
Nets – Full PCB signal
integrity simulation not necessary
– Not all traces are high speed
– Similar layouts require single simulation
– Good isolation in multilayer PCB minimizes crosstalk
Critical HighSpeed Nets
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Simulation Techniques• Lumped Element Models
(SPICE)– Generic (not pinout specific)– No physical length– Ideal elements– Must be highly distributed to
be accurate into GHz range– Appropriate for component
(capacitor, inductor, balun) models
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Simulation Techniques• Transmission Line
Models– Cross-sectional per
unit length model– Captures physical
properties of materials
– Appropriate for straight traces
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Simulation Techniques• 2.5D Electromagnetics
– Captures effects of bends and cross-talk
– Makes approximations for vias, conductor thickness, etc.
– Appropriate for planar geometries
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Simulation Techniques• Full 3D Electromagnetic
Simulation – Probe Cards– Connectors– Vias– Packages
• Most Rigorous Simulation Technique
• Captures All Losses of Physical Environment
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• Sum of Pieces:– 1dB Contactor– 1dB Board– 1dB Connectors,
Launches
• Collection of Pieces Approach Does Not Account for Transitions
+
FULL SYSTEM MODELING - INSERTION LOSS (dB)
-3
-2.5
-2
-1.5
-1
-0.5
0
0 5 10 15 20Frequency (GHz)
Loss
(dB
)
Case1: Trace + HFSS PROBE ONLY
Case2: Trace + SPICE Launch +HFSS PROBE ONLYCase3: HFSS Full Model
Case 1: 8.0 GHzCase 2 : 5.2 GHz
Case 3 : 4.4 GHz
Interface Simulation
≠ 3dB @ n GHz
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Case Study: High Speed Probe Card Test
• Testing of RF Input to DUT• 2.4 GHz Test Requirement• Will a Probe Card Support
This?
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Probe Card Test Interface• Physical Description of Components
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INSERTION LOSS (dB)
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0 2 4 6 8 10 12
Frequency (GHz)
Loss
(dB
)
Initial Design
Optimized Design
RETURN LOSS (dB)
-40
-35
-30
-25
-20
-15
-10
-5
0
0 2 4 6 8 10 12
Frequency (GHz)Lo
ss (d
B)
Initial Design
Optimized Design
Initial Design
Optimized Design
Increased Clearance
Connector Optimization• Signal Pin Creates Impedance
Mismatch with Standard Footprint• Optimizing PCB Ground Clearance
Diameter Improves Results
• Worst Case 1dB @ 1.5Ghz
• Best Case 1dB @ 6GHz
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Trace Length Loss• Often Major Contributor to Overall Loss• Must Correlate with Manufacturing Process• Worst Case (16”) 1dB @ 300 MHz• Best Case (2”) 1dB @ 5 GHz
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Optimization: Stub Removal• Stub – Full Length Via and Inner Layer Trace• Backdrill – Remove Via to Trace Layer• Worst Case 1dB @ 2 GHz• Best Case 1dB @ 8 GHz
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Probe Needle Optimization• The needles have
very high impedance, above 300 Ohms.
• Impedance can be lowered with epoxy to improve performance
• Worst Case 1dB @ 1 GHz• Best Case 1dB @ 1.4 GHz
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System Simulation• Model Includes:
– Connector• 3D EM simulation
– PCB traces • Transmission line models
– Balun • Manufacturer SPICE model
– Capacitors • Manufacturer SPICE model
– Vias • 3D EM simulation
– Probe card • 3D EM simulation
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System Performance
• Total System 3dB Loss point @ 1.9 GHz• Probe needles account for majority of loss
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Probe Needle Alternative• Spring Probe
– Probes 3mm vs needles 50mm– Probe impedance 80-120– Needle impedance 125-300
• Probes 1dB @ 21.4 GHz• Probes w/ 50mm trace 1dB @ 8.0GHz
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Probe Card vs. Contactor System Simulation Results
• Bandwidth– Probe Card 3dB @ 1.9 GHz– Spring Probe 3dB @ 6.1 GHz
• 10GB/s Eye Diagram– Probe Card 44ps rise-time– Spring Probe 24ps rise-time
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Going Forward• Other Variables Not Optimized:
– Via diameter, trace width, board material, clearance diameters, ground vias, package, etc.
• Future Work– Performance matrix for Engineers to quickly
determine loss given tester, probe type, board material
VIEW Pitch Probe PCB GND Trace Length -1dB -3dBX 0.4mm Gem040 N4000-13 GSSG Stripline 02in 3.8 12.1 15.9 53.9 103.7X 0.4mm Gem040 N4000-13 GSSG Stripline 12in 0.4 1.8 81.8 116.2 153.3
Insertion Loss 20-80 Output Rise TimeS12 10ps
INPUT50ps
INPUT100psINPUT
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Summary• System Performance Impacted by Choice
of Hardware Components and Design of Performance Board
• Simulation Can Optimize Performance Before Fabrication
• Simulation Reduces Lab Characterization and Re-spins and Provides Fastest Path to Production