At-Speed Test:Improving Defect Detection for Nanometer Designs
Jayant D’SouzaTechnical Marketing Engineer
At-Speed Test , SW DFT Symposium, May 20062
At-Speed Test MotivationAt-Speed Logic Test
— Defining At-Speed test— Path Delay & Transition Faults— At-Speed Patterns & Clocking— Issues & Solutions
At-Speed Memory Test— Memory BIST— Macro Testing
Conclusion
Agenda
At-Speed Test , SW DFT Symposium, May 20063
Why At-Speed Test?At-speed test detects the delays introduced by resistive defectsThis is necessary to maintain DPM rates in nanometer designsAt-speed testis a must!
Fabless Forum March 2003
Nvidia saw a 20X increase in speed-related defects moving from 180nm to 130nm.
G. Aldrich, B. Cory, “Improving Test Quality and Reducing Escapes,”Proc. Fabless Forum, Fabless Semiconduct Assoc., 2003, pp.34-35.
At-Speed Test , SW DFT Symposium, May 20064
Industry’s Thoughts on At-Speed Test“Delay defects are a critical consideration in designing test strategies to achieve outgoing quality goals …delay defects have typically represented 1% to 5% of the total defect population observed.Excerpts taken from IEEE Design & Test of Computers, Sept-Oct 2003“Delay Defect Characteristics and Testing Strategies”
“Delay defects are a critical consideration in designing test strategies to achieve outgoing quality goals …delay defects have typically represented 1% to 5% of the total defect population observed.Excerpts taken from IEEE Design & Test of Computers, Sept-Oct 2003“Delay Defect Characteristics and Testing Strategies”
“A study was performed on multiple ASICs to quantify the occurrence offrequency dependent defects with the yield loss and customer quality(DPM) reduction obtained by screening them. … In each case, the reduction in DPM is significant [33%-60%] …Excerpts taken from VTS 2003 paper entitled“Effectiveness Comparisons of Outlier Screening Methods for FrequencyDependent Defects on Complex ASICs”
“A study was performed on multiple ASICs to quantify the occurrence offrequency dependent defects with the yield loss and customer quality(DPM) reduction obtained by screening them. … In each case, the reduction in DPM is significant [33%-60%] …Excerpts taken from VTS 2003 paper entitled“Effectiveness Comparisons of Outlier Screening Methods for FrequencyDependent Defects on Complex ASICs”
“Each test in the MPC7410 test program uniquely detects a set of defectsthat cannot be detected by any other tests in the test program… bothDC and AC scan tests, all detect unique sets of defects.”
Excerpts taken from ITC 2002 conference paper entitled“Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits”
“Each test in the MPC7410 test program uniquely detects a set of defectsthat cannot be detected by any other tests in the test program… bothDC and AC scan tests, all detect unique sets of defects.”
Excerpts taken from ITC 2002 conference paper entitled“Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits”
At-Speed Test , SW DFT Symposium, May 20065
At-Speed Test MotivationAt-Speed Logic Test
— Defining At-Speed test— Path Delay & Transition Faults— At-Speed Patterns & Clocking— Issues & Solutions
At-Speed Memory Test— Memory BIST— Macro Testing
Conclusion
Agenda
At-Speed Test , SW DFT Symposium, May 20066
At-Speed ATPG
1 → 0 1 → 0
Test Path
Scan chains
Goal = test path for a falling edge propagation from 1 to 0ATPG will automagically determine appropriate values to
load scan chains and perform the test
At-Speed Test , SW DFT Symposium, May 20067
1 1 1
1
11
At-Speed ATPGHow it Works
Define values for starting value and to sensitize path
At-Speed Test , SW DFT Symposium, May 20068
Define values to cause launch eventNOW - all values are known to load the scan chain
At-Speed ATPGHow it Works
11
1
1
0
01
0
At-Speed Test , SW DFT Symposium, May 20069
1 → 0
1 → 1
1
0
01
00
1 → 0
Pulse clock in functional mode (SE=0) to launch eventThis causes the value change to start propagating through
the path
At-Speed ATPGHow it Works
1
At-Speed Test , SW DFT Symposium, May 200610
1 → 0
1 → 0
At-Speed ATPGHow it Works
Pulse clock in functional mode to capture value and verify that transition propagated in time
0
At-Speed Test , SW DFT Symposium, May 200611
At-Speed Test MotivationAt-Speed Logic Test
— Defining At-Speed test— Path Delay & Transition Faults— At-Speed Patterns & Clocking— Issues & Solutions
At-Speed Memory Test— Memory BIST— Macro Testing
Conclusion
Agenda
At-Speed Test , SW DFT Symposium, May 200612
Path Delay and Transition FaultsPath Delay fault model
— Tests combined delay through all gates of a path— Requires paths as input
Transition fault model— Tests for a gross delay potential at each gate terminal— Paths are automatically selected to test transition faults
Fault siteFault site
Faulty pathFaulty path
At-Speed Test , SW DFT Symposium, May 200613
SHIFT SHIFT
CLK
Capture
SE
Laun
ch
Cap
ture
SHIFT
Transition Fault Patterns
Transition fault patterns:— Launch-off shift
ATPG must switch scan enable at-speed (requires clock routing or pipelining of SE)Applies combinational ATPG
— Broadside or Launch-off capture Scan enable timing is not criticalApplies clock sequential ATPGActivated when clock-sequential depth > = 2 SHIFT
CLK
SE
Laun
ch
Cap
ture
SHIFT
...
...
SHIFTDead cycle
At-Speed Test , SW DFT Symposium, May 200614
Transition Testing
Launch-off Shift vs. BroadsideAdvantages
— Combinational ATPGFewer patterns, faster runtime
Disadvantages— Must disable scan enable
quicklyScan enable must be routed as a timing critical clockCan create non-functional patterns
Advantages— Fewer requirements on
the scan control logic and is usually easier
Shifting can be done at any speedScan enable does not have to be routed as a clock or pipelined
Disadvantages— Sequential ATPG (2
system clock cycles)More patterns, longer runtime
Most customers use broadside transition patterns!Most customers use broadside transition patterns!
At-Speed Test , SW DFT Symposium, May 200615
At-Speed Test MotivationAt-Speed Logic Test
— Defining At-Speed test— Path Delay & Transition Faults— At-Speed Patterns & Clocking— Issues & Solutions
At-Speed Memory Test— Memory BIST— Macro Testing
Conclusion
Agenda
At-Speed Test , SW DFT Symposium, May 200616
At-Speed Test Requires High Speed ClocksWhere do these clocks come from?
Automatic test equipment (ATE)— Requires high accuracy and tolerances— Usually only found on sophisticated
machines
Internal PLL or other clock generating circuitry
— Real functional clocks for testing— Allows use of less expensive ATE— ATPG must be able to produce desired
capture sequences from internal PLL
DesignCore
PLL PLLControl
At-Speed Test , SW DFT Symposium, May 200617
Improving At-Speed TestDealing with False Paths
False paths create unknown (X) states; impacts test coverage and compression Effective at-speed test must consider false and multicyclepaths during pattern generation
False Path
D
CK
Q
D
CK
Q
D
CK
Q
D
CK
Q
D
CK
Q
U1
U3 U6
U2
U5G6
G1
G2
G3
G4
G5
G7
Clk1
Techniques that just mask the observation point result in lower coverage and compression
ReadSDC
Auto identify false path: From U1/Q To U5/D
Through G3/A
untesteduntested
*Freescale: V. Vorisek et. Al, “Improved Handling of False and Multicycle Paths in ATPG”, VLSI Test Symposium, 2006
At-Speed Test , SW DFT Symposium, May 200618
New method: analysis based on path sensitizationOld method: cell constraint based masking
Improving the Quality of At-Speed Test
Test CaseTest CaseGate CountGate Count#Timing Exception#Timing Exceptionss
AA1.5M1.5M4.1K4.1K
BB3.7M3.7M1.3K1.3K
CC3.5M3.5M1.8K1.8K
DD3.8M3.8M1.3K1.3K
EE2.8M2.8M10.1K10.1K
Test coverage improvement [%] New New - Old +4.02%+4.02% +1.06%+1.06% +2.94%+2.94% +16.59%+16.59% +5.13%+5.13%
Old 12.6 20.5 13.5 17.1 30.0
NewNew 12.412.4 20.420.4 12.312.3 16.916.9 30.030.0
Old 0.34% 3.66% 1.25% 32.06% 3.02%
NewNew 0.08%0.08% 1.68%1.68% 0.29%0.29% 0.58%0.58% 0.93%0.93%Xs per pattern
Patterns [K]
At-Speed Test , SW DFT Symposium, May 200619
At-Speed Test MotivationAt-Speed Logic Test
— Defining At-Speed test— Path Delay & Transition Faults— At-Speed Patterns & Clocking— Issues & Solutions
At-Speed Memory Test— Memory BIST— Macro Testing
Conclusion
Agenda
At-Speed Test , SW DFT Symposium, May 200620
Don’t Over Test
Use broadside transition patterns instead of launch-off-shift
— Don’t exercise non-functional paths“No fault” test logic
— Compression logic— BIST— Boundary scan
Specify false and multicycle paths
At-Speed Test , SW DFT Symposium, May 200621
Multiple Clock Domains
What if design has 3+ clocks?ATPG tools must handle this automatically NOTE: most common practice is to test within each clock domain and not between domains
At-Speed Test , SW DFT Symposium, May 200622
Multiple Clocks and FrequenciesF1F1
F2F2
F3F3
F1F1
F1F1
F2F2 F3F3
F2F2
F3F3
××
××××
××
×××××× ××
××Capture domainCapture domain
Laun
ch d
omai
nLa
unch
dom
ain
At-Speed Test , SW DFT Symposium, May 200623
start_AC_test
Per Pattern “At-speed” Control
CONTROLLERCONTROLLER
PLLPLL
CLOCK GATINGLOGIC
CLOCK GATINGLOGIC
scan_in
Gated Clocks
Capture Sequence 3:
F1F1
F2F2
F3F3
0 10 1
Specify clock sequence
At-Speed Test , SW DFT Symposium, May 200624
Combining Stuck-At and At-Speed Tests
First idea— Add TDF after SAF
TDF = Time Delay FaultSAF = Stuck-at Fault
Pattern Count
% T
est C
over
age 100
50
TDFSAF
98%
85%
3k0k0
6k 9k
Pattern Count
% T
est C
over
age 100
50
TDF SAF
3k0k 6k 9k0
85%
98%91%Better idea
— Do TDF first— Fault grade for SAF
coverage— Create top-up SAF
At-Speed Test , SW DFT Symposium, May 200625
If Test Pattern Volume is Unacceptable
Don’t truncate!— Remember the reason you’re adding at-speed test is
to ensure qualityUse recommended flow with stuck-at generationRun compression on test set
— Important to get compression of both test data volume and test time
At-Speed Test , SW DFT Symposium, May 200626
At-Speed Test MotivationAt-Speed Logic Test
— Defining At-Speed test— Path Delay & Transition Faults— At-Speed Patterns & Clocking— Issues & Solutions
At-Speed Memory Test— Memory BIST— Macro Testing
Conclusion
Agenda
At-Speed Test , SW DFT Symposium, May 200627
Memory TestHow do you effectively test memories at-speed
At-speed ATPG can test logic around the memoriesAt-speed memory testing is necessary
At-Speed Test , SW DFT Symposium, May 200628
Memory Test
Testing typical memories— Industry-wide adoption of memory BIST— High quality memory BIST requires multiple
algorithms plus at-speed capabilitiesTesting very small (or performance critical) memories
— Various approaches employed (not testing being one of these)
— “Macro Testing” offers an ideal, high-quality test alternative to other approaches
At-Speed Test , SW DFT Symposium, May 200629
Macrotest
Memory BIST & MacrotestComplementary solutions for comprehensive memory testing
Preferred choice for comprehensive Built-in Self-test of embedded SRAM or ROM
Use when area or performance issues require a non-intrusive approach
MBIST
0110101
0110101
011010
110011
RAMLogic Logic
00101010101001101101010110001011001010011
At-Speed Test , SW DFT Symposium, May 200630
At-Speed Test MotivationAt-Speed Logic Test
— Defining At-Speed test— Path Delay & Transition Faults— At-Speed Patterns & Clocking— Issues & Solutions
At-Speed Memory Test— Memory BIST— Macro Testing
Conclusion
Agenda
At-Speed Test , SW DFT Symposium, May 200631
At-Speed test is necessary to ensure test qualityAt-Speed test must include logic and memory testFalse and multicycle paths must be handled by ATPG
Conclusion
At-Speed Test , SW DFT Symposium, May 200632
Mentor Supports At-Speed Test
FastScan: Industry leading ATPG with advanced at-speed testTestKompress: ATPG (including at-speed) capabilities of FastScan, with 100X compression
MBISTArchitect: Memory built-in-self-test with Full-SpeedTM operation (up to 1Ghz)MacroTest -- Scan-based testing for small memories, including at-speed
Memory TestMemory Test
Logic Test &Logic Test &CompressionCompression
At-Speed Test , SW DFT Symposium, May 200633
At-Speed Test , SW DFT Symposium, May 200634
At-Speed ATPG Reference InformationK. Kim, S. Mitra, P. Ryan, “Delay Defect Characteristics and Testing Strategies,” IEEE Design & Test of Computers, pp 8-16, Sept-Oct 2003.G. Aldrich, B. Cory, “Improving Test Quality and Reducing Escapes,” Proc. Fabless Forum, Fabless Semiconduct Assoc., 2003, pp.34-35.J. Boyer, and R. Press, “New Methods Test Small Memory Arrays,” Proc. Test & Measurement World, Reed Business Information, 2003, pp. 21-26.R. Wilson, “Delay-Fault Testing Mandatory, Author Claims,” EE Design, 4 Dec 2002.Tendolkar, N., “Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola’s Microprocessors Based on PowerPC Instruction Set Architecture”, VTS, 2002.J. Saxena et al., “Scan-Based Transition Fault Testing: Implementation and Low Cost TestChallenges,” Proc. Int’l Test Conf. (ITC 02), IEEE Press, 2002, pp. 1120-1129.Tendolkar, N., “At-Speed Testing of Delay Faults for Motorola’s MPC7400, a PowerPC™Microprocessor”, VTS, 2000.Bailey, B. et al., “Test Methodology for Motorola’s High Performance e500 Core Based on PowerPC Instruction Set Architecture”, ITC, 2002.Tendolkar, N., “A Study of FastScan Transition Fault ATPG Capability for PowerPCMicroprocessors”, Mentor Graphics User Group International Conf, 1998.Butler, K. M., “Estimating the Economic Benefits of DFT”, IEEE Design and Test of Computers, Jan-Mar 1999.Motorola At-Speed Test White Paper - www.mentor.com/dft