Download - Munnangi Anirudh VLSI Submit
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ADITYA SHARMA (B209004)
ANIKET DAS (B209006)
Expt No:1
Program : Full adder structural
-- Company:
-- Engineer:
--
-- Create Date: 11:48:06 10/17/2012
-- Design Name:
-- Module Name: faddstr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
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--use UNISIM.VComponents.all;
entity faddstr is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
cry : out STD_LOGIC);
end faddstr;
architecture structural of faddstr is
component andgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
op : out STD_LOGIC);
end component;
component xorgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
op : out STD_LOGIC);
end component;
component orgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
op : out STD_LOGIC);
end component;
signal s1,s2,s3,s4 : STD_LOGIC;
begin
l0: andgate port map(a,b,s1);
l1: andgate port map(b,c,s2);
l2: andgate port map(c,a,s3);
l3: orgate port map(s1,s2,s3,cry);
l4: xorgate port map(a,b,s4);
l5: xorgate port map(s4,c,s);
end structural;
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Program: Full adder behavioral
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:08:36 10/17/2012
-- Design Name:
-- Module Name: fadbeh - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fadbeh is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
ci : in STD_LOGIC;
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s : out STD_LOGIC;
cry : out STD_LOGIC);
end fadbeh;
architecture Behavioral of fadbeh is
begin
process(a,b,ci)
begin
if(a='0' and b='0' and ci='0')
then
s
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end Behavioral;
Program : Half adder structural
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:55:08 10/17/2012
-- Design Name:
-- Module Name: haddstr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity haddstr is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
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c : out STD_LOGIC);
end haddstr;
architecture Behavioral of haddstr is
component andgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
op : out STD_LOGIC);
end component;
component xorgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
op : out STD_LOGIC);
end component;
begin
l0: andgate port map(a,b,c);
l1: xorgate port map(a,b,s);
end Behavioral;
Program : Half adder behavioral
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:30:26 10/17/2012
-- Design Name:
-- Module Name: haddbeh - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
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-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity haddbeh is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
cry : out STD_LOGIC);
end haddbeh;
architecture Behavioral of haddbeh is
begin
process(a,b)
begin
if(a='0' and b='0' ) then
s
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Program : 3 to 8 decoder : structural
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:59:22 10/10/2012
-- Design Name:
-- Module Name: dec_3bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dec_3bit is
Port ( ip : in STD_LOGIC_VECTOR (2 downto 0);
op : out STD_LOGIC_VECTOR (7 downto 0));
end dec_3bit;
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architecture Behavioral of dec_3bit is
component and_3bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
op : out STD_LOGIC);
end component;
component negate is
Port ( ip : in STD_LOGIC;
op : out STD_LOGIC);
end component;
signal inip : STD_LOGIC_VECTOR(2 downto 0);
begin
l0: negate port map(ip(0),inip(0));
l1: negate port map(ip(1),inip(1));
l2: negate port map(ip(2),inip(2));
l3: and_3bit port map(inip(2),inip(1),inip(0),op(0));
l4: and_3bit port map(inip(2),inip(1),ip(0),op(1));
l5: and_3bit port map(inip(2),ip(1),inip(0),op(2));
l6: and_3bit port map(inip(2),ip(1),ip(0),op(3));
l7: and_3bit port map(ip(2),inip(1),inip(0),op(4));
l8: and_3bit port map(ip(2),inip(1),ip(0),op(5));
l9: and_3bit port map(ip(2),ip(1),inip(0),op(6));
l10: and_3bit port map(ip(2),ip(1),ip(0),op(7));
end Behavioral;
Program : 3 to 8 decoder behavioral
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:34:37 10/17/2012
-- Design Name:
-- Module Name: dec38beh - Behavioral
-- Project Name:
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-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dec38beh is
Port ( s : in STD_LOGIC_VECTOR (2 downto 0);
op : out STD_LOGIC_VECTOR (7 downto 0));
end dec38beh;
architecture Behavioral of dec38beh is
begin
process(s)
begin
if(s="000")
then
op
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elsif (s="011")
then
op
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_4bit is
Port ( ip : in STD_LOGIC_VECTOR (3 downto 0);
inp : in STD_LOGIC_VECTOR (15 downto 0);
op : out STD_LOGIC);
end mux_4bit;
architecture Behavioral of mux_4bit is
component and_5bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
e : in STD_LOGIC;
op : out STD_LOGIC);
end component;
component negate is
Port ( ip : in STD_LOGIC;
op : out STD_LOGIC);
end component;
signal inip : STD_LOGIC_VECTOR(3 downto 0);
begin
k0: negate port map(ip(0),inip(0));
k1: negate port map(ip(1),inip(1));
k2: negate port map(ip(2),inip(2));
k3: negate port map(ip(3),inip(3));
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l0: and_5bit port map(inip(3),inip(2),inip(1),inip(0),inp(0),op);
l1: and_5bit port map(inip(3),inip(2),inip(1),ip(0),inp(1),op);
l2: and_5bit port map(inip(3),inip(2),ip(1),inip(0),inp(2),op);
l3: and_5bit port map(inip(3),inip(2),ip(1),ip(0),inp(3),op);
l4: and_5bit port map(inip(3),ip(2),inip(1),inip(0),inp(4),op);
l5: and_5bit port map(inip(3),ip(2),inip(1),ip(0),inp(5),op);
l6: and_5bit port map(inip(3),ip(2),ip(1),inip(0),inp(6),op);
l7: and_5bit port map(inip(3),ip(2),ip(1),ip(0),inp(7),op);
l8: and_5bit port map(ip(3),inip(2),inip(1),inip(0),inp(8),op);
l9: and_5bit port map(ip(3),inip(2),inip(1),ip(0),inp(9),op);
l10: and_5bit port map(ip(3),inip(2),ip(1),inip(0),inp(10),op);
l11: and_5bit port map(ip(3),inip(2),ip(1),ip(0),inp(11),op);
l12: and_5bit port map(ip(3),ip(2),inip(1),inip(0),inp(12),op);
l13: and_5bit port map(ip(3),ip(2),inip(1),ip(0),inp(13),op);
l14: and_5bit port map(ip(3),ip(2),ip(1),inip(0),inp(14),op);
l15: and_5bit port map(ip(3),ip(2),ip(1),ip(0),inp(15),op);
end Behavioral;
Program : mux 8 to 1 behavioral
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:42:23 10/17/2012
-- Design Name:
-- Module Name: mux81beh - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux81beh is
Port ( ip : in STD_LOGIC_VECTOR (7 downto 0);
s : in STD_LOGIC_VECTOR (2 downto 0);
op : out STD_LOGIC);
end mux81beh;
architecture Behavioral of mux81beh is
begin
process(s,ip)
begin
if(s="000")
then
op
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op
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--use UNISIM.VComponents.all;
entity dec3812 is
Port ( ip : in STD_LOGIC_VECTOR (2 downto 0);
op : out STD_LOGIC_VECTOR (7 downto 0));
end dec3812;
architecture Behavioral of dec3812 is
component dec12 is
Port ( ip : in STD_LOGIC;
en : in STD_LOGIC;
o1 : out STD_LOGIC;
o2 : out STD_LOGIC);
end component;
signal mid : STD_LOGIC_VECTOR (5 downto 0);
begin
l0: dec12 port map(ip(2),'1',mid(0),mid(1));
l1: dec12 port map(ip(1),mid(0),mid(2),mid(3));
l2: dec12 port map(ip(1),mid(1),mid(4),mid(5));
l3: dec12 port map(ip(0),mid(2),op(7),op(6));
l4: dec12 port map(ip(0),mid(3),op(5),op(4));
l5: dec12 port map(ip(0),mid(4),op(3),op(2));
l6: dec12 port map(ip(2),mid(5),op(1),op(0));
end Behavioral;
Program: 8 to 1 mux using 2 to 1 mux : structural
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:04 10/17/2012
-- Design Name:
-- Module Name: mux81 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
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-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux81 is
Port ( ip : in STD_LOGIC_VECTOR (7 downto 0);
s : in STD_LOGIC_VECTOR (2 downto 0);
op : out STD_LOGIC);
end mux81;
architecture Structural of mux81 is
component mux21 is
Port ( s1 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
o : out STD_LOGIC);
end component;
signal mid :STD_LOGIC_VECTOR (5 downto 0);
begin
l0: mux21 port map(s(2),ip(7),ip(6),mid(0));
l1: mux21 port map(s(2),ip(5),ip(4),mid(1));
l2: mux21 port map(s(2),ip(3),ip(2),mid(2));
l3: mux21 port map(s(2),ip(1),ip(0),mid(3));
l4: mux21 port map(s(1),mid(0),mid(1),mid(4));
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l5: mux21 port map(s(1),mid(2),mid(3),mid(5));
l6: mux21 port map(s(0),mid(4),mid(5),op);
end structural;
TEST Bench Programs
Full adder :
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:38:46 10/17/2012
-- Design Name:
-- Module Name: F:/xilinxbaba/full_add/testfulladder.vhd
-- Project Name: full_add
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fulladd
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testfulladder ISEND testfulladder;
ARCHITECTURE behavior OF testfulladder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fulladd
PORT(
a : IN std_logic;
b : IN std_logic;
ci : IN std_logic;
s : OUT std_logic;
co : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal ci : std_logic := '0';
--Outputs
signal s : std_logic;
signal co : std_logic;
-- No clocks detected in port list. Replace below with
-- appropriate port name
--constant _period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
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uut: fulladd PORT MAP (
a => a,
b => b,
ci => ci,
s => s,co => co
);
-- Clock process definitions
-- _process :process
-- begin
--
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-- insert stimulus here
wait;
end process;
END;
Half adder
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:58:49 10/17/2012
-- Design Name:
-- Module Name: F:/xilinxbaba/full_add/teshadd.vhd
-- Project Name: full_add
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: halfadder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY teshadd IS
END teshadd;
ARCHITECTURE behavior OF teshadd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT halfadder
PORT(
A : IN std_logic;
B : IN std_logic;
S : OUT std_logic;
C : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
--Outputs
signal S : std_logic;
signal C : std_logic;
-- No clocks detected in port list. Replace below with
-- appropriate port name
-- constant _period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: halfadder PORT MAP (
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A => A,
B => B,
S => S,
C => C
);
-- Clock process definitions
-- _process :process
-- begin
--
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Decoder 3 to 8 :
--------------------------------------------------------------------------------
-- Company:-- Engineer:
--
-- Create Date: 11:07:48 10/10/2012
-- Design Name:
-- Module Name: F:/xilinxbaba/decoder3to8/test_3to8dec.vhd
-- Project Name: decoder3to8
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dec_3bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_3to8dec IS
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END test_3to8dec;
ARCHITECTURE behavior OF test_3to8dec IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dec_3bit
PORT(
ip : IN std_logic_vector(2 downto 0);
op : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal ip : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal op : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace below with
-- appropriate port name
-- constant _period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dec_3bit PORT MAP (
ip => ip,
op => op
);
-- Clock process definitions
-- _process :process
-- begin
--
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-- wait for _period/2;
-- end process;
--
-- Stimulus processstim_proc: process
begin
-- hold reset state for 100 ns.
wait for 1 ps;
ip
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-- Description:
--
-- VHDL Test Bench Created by ISE for module: mux81
--
-- Dependencies:--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testmux81 IS
END testmux81;
ARCHITECTURE behavior OF testmux81 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux81
PORT(
ip : IN std_logic_vector(7 downto 0);
s : IN std_logic_vector(2 downto 0);
op : OUT std_logic
);
END COMPONENT;
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--Inputs
signal ip : std_logic_vector(7 downto 0) := (others => '0');
signal s : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal op : std_logic;
-- No clocks detected in port list. Replace below with
-- appropriate port name
-- constant _period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux81 PORT MAP (
ip => ip,
s => s,
op => op
);
-- Clock process definitions
-- _process :process
-- begin
--
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s
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Full adder:
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Half adder :
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Decoder 3 to 8:
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7/29/2019 Munnangi Anirudh VLSI Submit
33/34
Multiplexer 8 to 1:
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7/29/2019 Munnangi Anirudh VLSI Submit
34/34