MOSFET
Small-Signal Model
Small-signal operation
Small-signal parameters
Small-signal models
Transistor Small-Signal Model
hibrid
Small-signal model (linear model) is necessary to deduce
vo as a function of vi
Necessity for the small-signal model (valid in the linear region around the OP)
The transistor for the small-signal regime:
small-signal parameters (differential parameters)
small-signal equivalent circuit of the transistor.
the values of the small-signal parameters depend on
the OP (they are calculated in the OP)
• transistor model for low and medium frequency:
input resistance
output resistance
controlled source showing the input-output transfer
• the model for high frequency will be enhanced with parasitic capacitances between its terminals
Small-signal operation
T – small-signal model
• two-port network
input resistance: ri
transfer: a controlled current source (by a voltage) – VCCS:
gmvi
output resistance: ro
Small-signal MOSFET
- linear model -
The full circuit of the amplifier with one MOST (dc biasing + small signal)
The small-signal equivalent circuit
results by setting to zero all dc voltage and/or current sources
CS topology
Small-signal parameters - MOSFET• Transconductance(shows the transfer from the variable input voltage to the variable output current)
cstv
gs
dcstv
GS
Dm DSDS v
i
v
ig
)(2)(( 2
ThGSQ
GS
ThGSm VV
v
Vvg
D
ThGS
DThGSm I
VV
IVVg 2
2)(2
Dm IL
WKg 2integrated transistors:
gsmd vgi MOSFET: voltage-controlled current source for small signal
2ThGSD Vvi
• Input resistancethe gate is electrically insulated from the rest of structure: the input resistance is infinite (open-circuit)
• Output resistance
cstv
d
dscstv
D
DS
o
o GSGS i
v
i
v
gr
1
the output characteristics are not perfectly horizontal, the drain current slightly increases with the drain to
source voltage at vGS=cst.
VA – Early voltage
A
DSThGSD
V
vVvi 1)( 2
D
Ao
I
Vr
𝒓𝒊 = ∞
MOSFETdc regime small-signal regime
2)( ThGSD VVI
gsmd vgi
D
Ao
I
Vr
gsThGSd vVVi )(2
D
DSO
I
VR
D
ThGS
D
ThGSm
IVV
I
VVg
22
2
Small-signal model of the MOSFET
• low and medium frequency:
D
Ao
I
Vr
• high frequency:
the parasitic capacitances appear between terminals; typically pF or fractions of pF
D
ThGS
D
ThGSm
IVV
I
VVg
22
2
hibrid
linear models (valid around OP)
Numerical examples
ß=2mA/V, VA=100V; biased at ID=2mA.
k502
100
D
Ao
I
VrmS42222 Dm Ig
ß=2mA/V2, VTh=1.5V VA=100V ; biased at VGS=2.5V.
mS4)5.15.2(222 ThGSm VVg
Case 1
Case 2
mA2)5.15.2(2)( 22 ThGSD VVI k502
100
D
Ao
I
Vr
K=100μA/V2 , W/L=1, VA=100V; biased at ID=100μA.
mS14.0100110022 Dm IL
WKg
MΩ11.0
100
D
Ao
I
Vr
Case 3