Monolithic pixel detectors with 0.2 m FD-SOI pixel process technology
Toshinobu Miyoshi on behalf of SOIPIX collaborationHigh Energy Accelerator Research Organization(KEK)
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@Vienna University of Technology
The Vienna Conference on Instrumentation (VCI) 2/11-2/15 2013
Electronics session2/14 14:50-15:15
Karlskirche
Outline
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Introduction of SOI detectorsBrief review of our activities: measurement of X-rays/charged particles- INTPIX4,INTPIX5, XRPIX1b, FPIX1, INTPIX3eMain topics:(1) CZn/FZn sensors study(2) Double SOI circuit/sensor studySummary
SOI Wafer ProductionSmart cutTM by SoitecSpecify wafer resistivity: High resistivity (High R) wafer --- Sensor Low resistivity (Low R) wafer --- CMOS
Development of the SOI monolithic pixel detector has been started since 2005 as a project of the KEK Detector Technology Project (KEK DTP)Use Lapis Semiconductor Co Ltd. 0.2 m FD-SOI pixel process
Initial silicon
Oxidation
Implantation
Splitting
High R
Low R
Cleaning and bonding
SOI wafer
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•No mechanical bump bonding. Fabricated with semiconductor process only high reliability and low cost • Fully depleted (thick & thin) sensing region with low sense node capacitance (~10fF@17m pixel) high sensor gain • Wide temperature range (4-570K)• Low single event cross section• Technology based on industry standards
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The features of SOI monolithic pixel detector
SiO2
High R Si
Low R Si
Process
(Lapis Semiconductor Co. Ltd.)
0.2m Low-Leakage Fully-Depleted (FD) SOI CMOS
1 Poly, 5 Metal layers (MIM Capacitor and DMOS option)
Total thickness above top Si (SOI layer) ~ 9 m
Core (I/O) voltage : 1.8 (3.3) V
SOI wafer
(200 mm
=8 inch)
Top Si : Cz, ~18 -cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick
Handle wafer thickness: 725m thinned up to 300m (Lapis)
or commercial process ~50 m (then, backside process…) Handle wafer: CZn ~ 700 -cm (Default)
FZn > 3 k -cm (2009-)
FZp ~ 25 k-cm (2010-)
Double SOI (CZn) (2012-)
Backside process
Mechanical Grind Chemical Etching Back side Implant Laser Annealing Al plating
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Process
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Multi Project Wafer (MPW) run• KEK organizes MPW runs twice a year• Mask is shared to reduce cost of a design• Including pixel detector chip and SOI-CMOS circuit chip ・ University & institutionKEK, FNAL, LBNL, AIST, CNS, Kyoto Univ., Tohoku Univ., Univ. of Tsukuba, RIKEN-XFEL, JAXA, Krakow, Hawaii, IHEP, and more…
Lapis Semiconductor Co. Ltd. ,Lapis Semiconductor Miyagi Co. Ltd. , T-Micro Co. Ltd., Rigaku Co. Ltd
Supporting companies
FY12-1
FY12-2
24.6 mm
30.8
mm
INTPIX5
INTPIX3g
FPIX1
FY11
D-SOI TEG
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FY09-1INTPIX3bINTPIX4XRPIX1
2005 2006 2007 2008 2009 2010 2011 2012
FY05MPW(VDEC)
PIXELTEG(INTPIX)
Development history: SOI Integration type pixel detector
FY06KEKMPW0.15mProcess
INTPIX1
FY07KEKMPW0.2mProcess
INTPIX2
FY08INTPIX3a
FY09-2INTPIX3c
FY10-1INTPIX3eDIPIX
FY10-2INTPIX3fXRPIX1b
FY11INTPIX3gINTPIX5FPIXXRPIX2
Buried P Well(BPW)
FZ wafer(FZn)
3D integration
FZ wafer(FZp)BNW,
Nested Well process
Double SOI
New!
New!
New!
New!
FY12-1LHDPIXINTPIXhXRPIX2b
FY12-2LHDPIX2INTPIXh2XRPIX3INTPIX6
20m
17m
14m
16m
12m
8m
Pixel size
KEK is working on integration-type and counting-type / digital (binary) pixel detectors
* Only integration-type detectors are shown
18m
30m
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X-ray imaging (INTPIX4) , 3 images are combined
Measurement of X-rays
Compton electron detection (INTPIX4) X-ray spectrum (XRPIX1b)
Kyoto Univ. & KEK
Dried fish
For astronomical mission
* CZn sensor
Sensor gain 6V/e-
10 lines (RA141-151) profile
FPIX1 – The smallest pixel in KEK sensors
2.048mm
2000 event accumulationCr target 30kV-60mA(1.8kW MAX)FPIX1 (CZn-260um) Vdet=70V (partially depleted)Temperature 15deg.
10 9 87JIMA RT RC-05 (1m-Au absorber)
3 slits/group, 2x2mm area, 3-50m
CARA
CA
X-ray image
8m lines can be seen 9
CTF>20%
8m
x103
Pixel size 8m, 512x512, effective area 4.096 x 4.096 mmNo STORE, no storage capacitor
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Measured at Research Center for Charged Particle Therapy, NIRS, Chiba, JapanINTPIX5 low-gain mode, 64x64 pixels are used
Carbon beam
Measurement of charged particles
particles from Am-241
INTPIX5 with high-gain mode
0.1mm
1mm
Pixel size 12m
* CZn sensor
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It was used for high-energy particle beam test in 2011
4 layers of INTPIX3e(pixel size = 16 x 16 m)
From master thesis by Katsurayama(Tohoku Univ.)
An example of residual distribution
CERN SPS NORTH H4-H6 55%, p 39%, K 5%120 GeV
Residual 1-4 layers is 2-4m in
From master thesis by Shinsho (Univ. of Tsukuba)
The chip was thinned by Nihon Exceed
CZn-INTPIX3e50m-thick
S/N ~ 15
260m-thick CZn INTPIX3e
MIP spectrum
INTPIX3e – general purpose integration-type pixel detector
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INTPIX5 (FY11)1408 x 896 pixelsPixel size 12 x 12 mEffective area 16.896 x 10.752 mm
12m
Pixel layout
Pixel circuit
Sense node
CZn/FZn sensor study
No breakdown up to 400VLeakage current is higher for CZn-INTPIX5Leakage current of FZn sensor became lower thanks to Lapis back processing
CZn
FZn
2012
~10000e-/200us/pixel
~10e-/200us/pixel
Main topics (1)
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KEK-PF BL-14B monochromatic X-ray E=16.1 keVUse NTT-AT test chartFront and back illuminationCZn 260m-thick INTPIX5 (100V, partial depletion)FZn 500m-thick INTPIX5 (170V, full depletion)
Spatial resolution study @ KEK-PF
20LP/mm(25 m slits)
25LP/mm(20 m slits)
31.25LP/mm(16 m slits)
~2 mm
NTT-AT X-ray chart
130-3050CZn-INTPIX5-Front
320-4220CZn-INTPIX5-Back
-480-7900
-670-7920
FZn-INTPIX5-Front
FZn-INTPIX5-Back
Spatial resolution of CZn & FZn INTPIX5KEK-PF BL14A monochromatic X-ray Energy ~ 16 keV
25m 16m20m
16 m slits can be seen for all the images.
25m 16m20m
25m 16m20m 25m 16m20m
image
1D profile
500
1000
~0
~0
100V
, par
tial
dep
leti
on10
0V, p
arti
al d
eple
tion
170V
, ful
l dep
leti
on17
0V, f
ull d
eple
tion
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Current issues
The back gate effect --- BPW/BNW process is a solutionCharge trap at BOX --- TID effectCross talk (Under testing. I don’t show any results today)
Utilization of Double SOI (D-SOI) waferA suggestion
Y. Arai et al., NIM A Vol. 636, Issue 1, Supplement, 21 April 2011, Pages S31–S36
Main topics (2) Double SOI circuit/sensor study
Double SOI Wafer Production
Initial silicon
Oxidation
Implantation
Cleaning and bonding
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Additional shield layer
SEM image
SOI wafer
1st trial.The parameters are not optimized.
The 1st TEG/sensor chips were received on Oct. 2012.
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Breakdown
Double SOI sensor test status (2012.10 ~)
Vdet ring(+HV)
Bias ring(0V)
Remove SOI2 between them
Improvement
Charge collection efficiency reduction between pixels BNW between pixels (INTPIX3g, PIXOR)
Pixel(n) Pixel(n+1)
Fixed (-2V)
+45V(Vdet)
BNW
BPW
X-ray image (0.4x0.4 mm beam spot)12keV monochromatic X-ray @KEK-PF BL 14A
DSOI-INTPIX3g
The 2nd process(MX1501,MX1542)
Issue 1 Lower breakdown voltage
Issue 2 charge collection inefficiency
,remove DSOI between pixels, or use p-wafer
X-ray beam spot
The 2nd test chip will be received in FY2013
NMOS
PMOS
Vsoi2
Vsoi2
N33_IONVT_ST2_L0.4_w5
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Vsoi2=0.0[V]
Vsoi2=-1.0[V] Vsoi2=-2.0[V]
Vsoi2=0.0[V]
Vsoi2=-1.0[V]
Vsoi2=-2.0[V]
[kGy]
Vth[
V]
Univ. of TsukubaHara, Honda, Ishibashi
Preliminary
Co-60 gamma-ray TID test @ JAERI/Takasaki
NMOS is ON at more than ~ 400 krad with Vsoi2=0VNMOS works at 10Mrad with Vsoi2=-2VPMOS works at 10 Mrad
10 102 103 104 [krad]
Double SOI Test Element Group (TEG) chip (AIST & KEK) During irradiation, all the contacts are set to GND.
Dose
X-ray irradiation Every 10/20/60 sec
Single SOI :10 sec x 6 timesDouble SOI :10 sec x 20 times20 sec x 5 times60 sec x 10 times
Measurementbeam-on/off ADC output in a pixel
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SOI sensor : INTPIX3gUse 128x128 pixels Single SOI CZn / Double SOI CZnX-ray target
Cu K 8.1keV30kV-60mA
IntensityMeasured by 300um-thickSilicon PIN PD@30kV-60mACurrent 885nA (Error 3%)
BNW ring is overlapped with BPW
X-ray irradiation test
~16cm
X-ray slit (1mm x 1mm)
Experimental setup
18m
In double SOI, V(middle SOI) = -2V
X-ray
The firstIrradiation(9krad/10sec)
After 18krad
After 27krad
After 36krad
After45 krad
Single SOI CZn (HR1, 3JA) Total dose 54 krad Signals disappeared
Preliminary results of high dose X-ray irradiation test
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Caution!: INTPIX3g design has problem and has very low dynamic range!
The firstIrradiation(9krad/10sec)
After 90krad
After 180krad
After 360krad
After 801 krad
D-SOI CZn (6JA) Total dose 810 kradSignals still appear(Dynamic range changed narrower)
* Middle SOI voltage = -2V
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9krad/10sec/each
Preliminary results of radiation tolerance study
Saturation level
Saturation level
*Offset is arbitrary
Signals disappeared!
Dynamic range became narrower, but signals still appeared.
9krad/10sec x 20 times 9krad/20sec x 5 times 9krad/60sec x 10 times
Reference channel = (50,50)
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Preliminary results of radiation tolerance study
Signals disappeared!
Dynamic range became narrower, but signals still appeared.
Double SOI sensor worked after 800 krad irradiation.Dynamic range (eventually transistor parameters) was changed.
Output at the Beam-off period just after irradiation
60sec/each
20sec/each
10sec/each
One solution: reduce reset voltage because the SF transistor VTH was shifted.
SummarySOI monolithic detector has many attractive features.MPW runs twice a yearProcess was improved and several wafers are available.Integration type pixel detectors- High gain with smaller pixel size w/o CSA-Good energy resolution-Good spatial resolution (CZn/FZn)- Charged particles were detected by thin CZn sensors- Thick FZn wafer is suit for hard-X-ray detectionCurrent issues-The back-gate effect BPW/BNW process, double SOI-Crosstalk double SOI, under testing-Radiation hardness Transistors and sensors on double SOI wafer had radiation tolerance with middle SOI potential control.
FY2013Test of several types of wafers Optimization of pixel layout with double SOIApplication experiment 23
Figlmuller Schnitzel
8 inch SOI wafer
(by size!)
SOIPIX CollaborationKEK : Y. Arai (Project Leader) , Y. Unno, Y. Ikegami, T. Tsuboyama, T. Kohriki, Y. Ikemoto, T. Miyoshi, K. Tauchi, R. Ichimiya, Y. FujitaGrad. Univ. for Adv. Stu. D. Nio, A. TakedaTsukuba Univ. : K. Hara, T. Ishibashi, Y. HondaOsaka Univ.: K. HanagakiTohoku Univ. : H. Yamamoto, Y. Ono, S. ShinodaCNS/Tokyo Univ. : H. Hamagaki, Y. SekiguchiKyoto Univ. : T. Tsuru, S. G. Ryu, S. NakashimaKyoto Univ. of Education: R. Takashima, S. Moritake JAXA/ISAS : H. Ikeda, T. WadaRIKEN X-FEL : T. Hatsui, T. Kudo, M. Omotani, S. OnoHawaii: G. Varner, M. Cooney, H. Hoedlmoser, J. Kennedy, HB SahooLBNL : M. Battaglia, P. Denes, C. Vu, D. Contarato, L. Glesener FNAL : R. Yarema, R. Lipton, G. Deptuch, M. Trimpl, F. F. KhalidKrakow IFJ/AGH: P. Kapusta, I. Ahmed, M. IdzikINFN Padova: D. Bisello, S. Mattiazzo, D. Pantano, P. Giubilato, AIST: M. Ohno, Y. Igarashi, M. Yanagihara, H. Tadokoro, T. ChibaIHEP: Y. LuLapis Semiconductor Co. Ltd. : M. OkiharaLapis Semiconductor Miyagi Co. Ltd. : H. Kasai
24Thank you for your attention!
2012.3 ver.
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Supplements
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BOX
BOXMiddle SOI (shield layer)
“SOI2”=Floating or 0V
n- bulk
P+
NMOS Tr
AIST double SOI TEGNMOS #1 Tr IdVg, Vds=1.8V
SOI2=floating
SOI2=0V
Double SOI effectiveness study
Middle SOI layer blocks the back-gate effect. We expect the middle SOI blocks sensor cross-talk.
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Back bias (0-25V)
Back bias
Back bias
N33_IONVT_ST2_L0.4_w5
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Dose
NMOS
Vsoi2=0[V] Vsoi2=-1[V] Vsoi2=-2[V]
Honda (Univ. of Tsukuba)
IdVgs curve with dose