Download - MobileMAN Hardware development for the MAC module current state and outlook IAB meeting By
Apu, IDe, 2004.06.07 MobileMAN meeting, Helsinki Page 1/18
MobileMAN Hardware development for the MAC module
current state and outlookIAB meeting
By
Ralph Bernasconi, Ivan Defilippis, Silvia Giordano, Alessandro Puiatti
SUPSI Manno
Helsinki, June 7-8 2004
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Contents
• Introduction• Completed work• Current work• Next steps• Data structure description• Questions?
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IntroductionProject’s SUPSI-DIE goals (reminder)
• Provide flexible development- and test-bed for enhanced WLAN protocol (CNR)
• Bursty responsive MAC• Better contention scheme (backoff); avoid collisions even
for dense and active networks• Ensure compatibility with 802.11x
• Provide few samples to partners• Provide inputs for new standard
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• Analysis of the Market for the 802.11 implementations• Available solutions?• Which solution best suits our needs? Criteria are:
- Cost- Reliability- Flexibility- Access to the software code- Access to the firmware- Easy development environment- Secure and prompt technical support
Completed work (1/8)
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• Alternatives for development: • Start from scratch:
- Implementation of a complete chain: MAC - BB - RF
• Start “in the middle”:- Implementation of the MAC only
• Start from an already implemented solution:- Change software and firmware for our purpose
Completed work (2/8)
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• Selected solution
• Start “in the middle”
• BB and RF already developed by Elektrobit AG:
- DT20 Modem (Intersil Prism-I chipset)
• Implement MAC on a DSP microcontroller
- TI C6713 board (Texas Instruments)
Completed work (3/8)
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Level-Switch interfaces
DT20 - Modems
TI C6713 boards
JTAG interface
• Development system
Completed work (4/8)
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• Deep analysis of the 802.11 standard• Procedures and flowchart for the Tx/Rx further implementation
• Implementation on the DSP board• CRC on FPGA• Tx/Rx between MAC and BB• Channel Sensing mechanism on MAC (MAC – RF)• MAC Tx mechanism• MAC Rx mechanism
Completed work (6/8)
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• Implementations on the DSP board (cont.)• Standard backoff mechanism• Regular 802.11 frame generation• Fragmented frame generation• RTS/CTS/DATA/AK handshake• MAC Address recognition• Channel contention
Completed work (7/8)
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• Tests done (2 systems/boards)• Stress tests in Tx between boards connected by cable• Stress tests in Rx between boards connected by cable• Stress tests in Tx/Rx between boards connected by cable• Stress tests in Tx/Rx between boards in wireless mode
- Standard backoff tested successfully- Fragmented Tx/Rx tested successfully- RTS/CTS/DATA/AK handshake tested successfully
Completed work (8/8)
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• Assembly of the 3rd system/board• Definition of the host interface mechanism
(via IEEE-1394/FireWire)• Definition of the standard packets data-structure• Definition of data-structure extensions for cross-
layering implementation
Current work
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• Implementation on the DSP• NAV (Network Allocation Vector)
• Test of a 3 nodes network (with above functionality)• Implementation and test of the host interface mechanism• Implementation and test of the standard packets data-structure• Implementation and test of data-structure extensions for cross-
layering• Implementation and test of the modified (CNR-Pisa) backoff
mechanism
Next steps
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• Memory slotted in parameterized slot length (default frame max length)
• Descriptor mechanism for handling data• Different queues for managing data transfer:
• From MAC to PHY and from PHY to MAC• From MAC to Host and from Host to MAC
• Implementation of priority mechanisms for each queue• Control flags in descriptor in which:
• DATA = Frame• DATA = parameters for/from cross-layering
Data Structure description (1/4)
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MAC header x
FCS x
Frame
Memory Data Area
MAC(DSP)
Frame body x+1
Frame body x
Descriptor x
Descriptorx+1
End HMQ
Descriptor x+n+1
MAC h. y+n-1
Frame body y+n-1
FCS y+n-1
MAC h. y+n
Frame body y+n
FCS y+n
Descriptorx+n
Frame body x+n
Frame body x+n+1Descriptor y+n-1
Descriptory+n
End MPQ
MAC to PHY Queue
BeginHost to MAC
Queue
BeginHost to MAC
Queue
End MPQ
End HMQ
MAC h. y+n+1
FCS y+n+1
Frame body y+n+1
Descriptor y+n+1
Data Structure description (2/4)
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MAC header y
FCS y
Frame
Memory Data Area
MAC(DSP)
Frame body x+1
Frame body x
Descriptor x
Descriptorx+1
End MHQ
MAC h. y+1
Frame body y+1
FCS y+1
MAC h. y+2
Frame body y+2
FCS y+2
Descriptorx+n
Frame body y
Descriptory+2
Descriptor y+1
End PMQ
PHY to MAC Queue
BeginMAC to Host
Queue
Begin
Descriptor y
Frame body x+n
End MHQ
PHY to MAC Queue
Begin
Frame body x+n+1
Descriptor x+n+1
Data Structure description (3/4)
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Management of queues with different levels of priority
Descriptor 1Pn
Descriptor 1Pn-1
End Q
DescriptorP0
Descriptor 2Pn
Descriptor 3Pn
Descriptor 4Pn
Descriptor kPn
End Q-PnDescriptor 2
Pn-1Descriptor h
Pn-1End Q-Pn-
1
Descriptor 2P0
Descriptor 3P0
Descriptor gP0
End Q-P0
Data Structure description (4/4)