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ì Computer Systems and Networks ECPE 170 – Jeff Shafer – University of the Pacific
MIPS Assembly
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Lab Schedule
AcAviAes ì This Week
ì MIPS discussion ì PracAce problems
(whiteboard) ì Using the QtSPIM
simulator ì MIPS funcAons
Assignments Due ì Lab 10
ì Due by Apr 14th 5:00am
ì Lab 11 ì Due by Apr 23rd 5:00am
ì Lab 12 ì Due by May 1st 5:00am
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Person of the Day – John Cocke
ì Computer architecture pioneer ì “Father of RISC Architecture” ì Developed IBM 801 processor,
1975-‐1980
ì Winner, ACM Turing Award, 1987
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RISC = Reduced InstrucHon Set CompuHng
Achieve higher performance with simple instrucAons that execute faster
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Person of the Day – John Hennessy
ì Computer architecture pioneer
ì Popularized RISC architecture in early 1980’s
ì Founder of MIPS Computer Systems in 1984
ì Currently president of an obscure school: Stanford University
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Class to Date
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Human (C Code)
Compiler (Assembly code)
Compiler (Object file / binary code)
Linker (Executable program)
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Class Now
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Human (Assembly code)
Assembler (Object file / binary code)
Linker (Executable Program)
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ì MIPS
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MIPS Overview
ì Family of computer processors first introduced in 1981
ì Microprocessor without Interlocked Pipeline Stages ì Original acronym ì Now MIPS stands for nothing at all…
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MIPS Products
ì Embedded devices ì Cisco/Linksys routers ì Cable boxes ì MIPS processor is buried inside System-‐on-‐a-‐Chip (SOC)
ì Gaming / entertainment ì Nintendo 64 ì PlaystaAon 2, PSP
ì Computers? ì Not so much anymore… ì SGI / DEC / NEC workstaAons back in 1990’s
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MIPS Design
ì RISC – What does this mean? ì Reduced InstrucAon Set CompuAng ì Simplified design for instrucAons ì Use more instrucAons to accomplish same task
ì But each instrucAon runs much faster!
ì 32 bits (originally) – What does this mean? ì 1 “word”= 32 bits ì Size of data processed by an integer add instrucAon ì New(er) MIPS64 design is 64 bits, but we won’t
focus on that
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ì MIPS Assembly Programming
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Quotes – Donald Knuth
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“People who are more than casually interested in computers should have at least some idea of what the underlying hardware is like. Otherwise the programs they write will be pretty weird.” ���– Donald Knuth
This is your moAvaAon in Labs 10 and 11!
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Why Learn Assembly Programming?
ì Computer Science track ì Understand capabiliAes (and limitaAons) of physical
machine ì Ability to opAmize program performance (or
funcAonality) at the assembly level if necessary
ì Computer Engineer track ì Future courses (e.g. ECPE 173) will focus on processor
design ì Start at the assembly programming level and move into
hardware ì How does the processor implement the add instrucAon? ì How does the processor know what data to process?
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Instruction Set Architecture
ì InstrucHon Set Architecture (ISA) is the interface between hardware and sojware ì Specifies the format of processor instrucAons ì Specifies the format of memory addresses
(and addressing modes) ì Specifies the primiAve operaAons the processor can
perform
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Instruction Set Architecture
ì ISA is the “contract” between the hardware designer and the assembly-‐level programmer
ì Documented in a manual that can be hundreds or thousands of pages long ì Example: Intel 64 and IA-‐32 Architectures Sojware
Developers Manual ì hkp://www.intel.com/content/www/us/en/processors/
architectures-‐sojware-‐developer-‐manuals.html ì No joke – the manual PDF from August 2012
is 3020 pages long!
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Instruction Set Architecture
ì Processor families share the same ISA
ì Example ISAs: ì Intel x86 ì Intel / AMD x86-‐64 ì Intel Itanium ì ARM ì IBM PowerPC ì MIPS
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All completely different, in the way that C++, Java, Perl, and PHP are all different…
… and yet learning one language makes learning the next one much easier
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Why MIPS?
ì Why choose MIPS? ì The MIPS ISA manual (volume 1, at least) is a svelte
108 pages! ì Extremely common ISA in textbooks ì Freely available simulator ì Common embedded processor ì Good building-‐block for other RISC-‐style processors ì Aligns with ECPE 173 course
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Arithmetic Instructions
ì AddiAon
ì SubtracAon
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add <result>, <input1>, <input2>
sub <result>, <input1>, <input2>
OperaAon / “Op code” Operands
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Task : Write Code
ì Write MIPS assembly for
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f = (g+h) – (i+j)
add temp0, g, h add temp1, i, j sub f, temp0, temp1
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CongratulaHons!
You’re now an assembly programming expert!
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Data Sources
ì Previous example was (just a liHle bit) fake… ì We made up some variables:
temp0, temp1, f, g, h, i, and j ì This is what you do when programming in C++
(or any high level language)
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Problem: You can’t make up variables in assembly! (as least, not in this fashion)
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Data Sources
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Where can we explicitly place data in assembly programming?
CPU
ALU
1. Registers ì On the CPU itself ì Very close to ALU ì Tiny ì Access Ame: 1 cycle
2. Memory ì Off-‐chip ì Large ì Access Ame: 100+ cycles
Cache Memory
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Aside – Cache
ì Review: Does the programmer explicitly manage the cache?
ì Answer: No! ì The assembly programmer just reads/writes
memory addresses ì Cache is managed automaAcally in hardware ì Result: Memory appears to be faster than it really is
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ECPE 71
ì From your knowledge of ECPE 71 (Digital Design), how would you construct a register?
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Flip Flops! (D Flip Flop shown)
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ECPE 71 – Group of Registers
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Registers
ì MIPS design: 32 integer registers, each holding 32 bits ì “Word size” = 32 bits
ì This is only 19 – where are the rest of the 32? ì Reserved by convenLon for other uses ì We’ll learn a few more later…
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Name Use
$zero Constant value: ZERO
$s0-$s7 Local variables
$t0-$t9 Temporary results
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Task : Write Code
ì Write MIPS assembly using registers for:
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f = (g+h) – (i+j)
Code:
add $t0, $s0, $s1 add $t1, $s2, $s3 sub $s4, $t0, $t1
Map: $s0 = g $s1 = h $s2 = i $s3 = j $s4 = f
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More Arithmetic Instructions
ì Add Immediate
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addi <result>, <input1>, <constant>
Can be a posiAve or negaAve number!
Register Register
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Task : Write Code
ì Write MIPS assembly using registers for:
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f = g+20
Code:
addi $s0, $s1, 20 Map:
$s0 = f $s1 = g
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Memory
ì Challenge: Limited supply of registers ì Physical limitaAon: We can’t put more on the
processor chip, and maintain their current speed ì Many elements compete for space in the CPU…
ì SoluAon: Store data in memory
ì MIPS provides instrucAons that transfer data between memory and registers
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Memory Fundamentals
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MIPS cannot directly manipulate data in memory!
Data must be moved to a register first! (And results must be saved to
a register when finished)
This is a common design in RISC-‐style machines: a load-‐store architecture
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Memory Fundamentals
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Yes, it’s a pain to keep moving data between registers and memory.
But consider it your moLvaLon to reduce the number of memory accesses. That will improve program performance!
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Memory Fundamentals
ì Four quesAons to ask when accessing memory: 1. What direcHon do I want to copy data?
(i.e. to memory, or from memory?) 2. What is the specific memory address? 3. What is the specific register name? (or number) 4. How much data do I want to move?
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CPU
Memory – Fundamental Operations
Load ì Copy data from
memory to register
Store ì Copy data from
register to memory
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CPU Memory Memory
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Memory – Determining Address
ì There are many ways to calculate the desired memory address ì These are called addressing modes ì We’ll just learn one mode now:
base + offset
ì The base address could be HUGE! (32 bits) ì We’ll place it in a register
ì The offset is typically small ì We’ll directly include it in the
instrucAon as an “immediate”
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Memory
0 1 2 3 4
Base
Offset
MIPS notaHon: offset(base)
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Memory – Register Name
ì What is the name of the register to use as either the data desAnaAon (for a load) or a data source (for a store)?
ì Use the same register names previously learned
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Memory -‐ Data Transfer Size
ì How much data do I want to load or store? ì A full word? (32 bits) ì A “half word”? (16 bits) ì A byte? (8 bits)
ì We’ll have a different instrucHon for each quanHty of data
ì No opAon to load an enAre array! ì Will need a loop that loads 1 element at a Ame…
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Memory – Data Transfer Instructions
ì Load (copy from memory to register)
ì Store (copy from register to memory)
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lw <reg>, <offset>(<base addr reg>)
lb <reg>, <offset>(<base addr reg>)
sw <reg>, <offset>(<base addr reg>)
sb <reg>, <offset>(<base addr reg>)
Word:
Byte:
Word:
Byte:
Register Memory LocaAon
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Example
ì What will this instrucHon do?
ì Load word copies from memory to register: ì Base address: stored in register $s2 ì Offset: 20 bytes ì DesAnaAon register: $s1 ì Amount of data transferred: 1 word (32 bits)
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lw $s1, 20($s2)
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Task : Write Code
ì Write MIPS assembly for:
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g = h + array[16] (Array of words. Can leave g and h in registers)
Code: # Assume $s3 is already set
lw $t0, 16($s3) add $s1, $s2, $t0
Map: $s1 = g $s2 = h $s3 = base address of array
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Memory Address
ì Slight flaw in previous soluAon ì The programmer intended to load the 16th array
element ì Each element is 4 bytes (1 word) ì The offset is in bytes ì 16 * 4 = 64
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Correct Code: # Assume $s3 is already set
lw $t0, 64($s3) add $s1, $s2, $t0
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Task : Write Code
ì Write MIPS assembly for:
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array[12] = h + array[8] (Array of words. Assume h is in register)
Code: # Assume $s3 is already set
lw $t0, 32($s3) add $t1, $s2, $t0 sw $t1, 48($s3)
Map: $s2 = h $s3 = base address of array $t1 = temp
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Task : Write Code
ì Write MIPS assembly for:
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g = h + array[i] (Array of words. Assume g, h, and i are in registers)
Code: # "Multiply" i by 4 add $t1, $s4, $s4 # x2 add $t1, $t1, $t1 # x2 again # Get addr of array[i] add $t1, $t1, $s3 # Load array[i] lw $t0, 0($t1) # Compute add add $s1, $s2, $t0
Map: $s1 = g $s2 = h $s3 = base address of array $s4 = i
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Aside – Compiler
ì When programming in C / C++, are your variables (int, float, char, …) stored in memory or in registers?
ì Answer: It depends
ì Compiler will choose where to place variables ì Registers: Loop counters, frequently accessed scalar
values, variables local to a procedure ì Memory: Arrays, infrequently accessed data values
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ì MIPS Branches / Loops
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Branches, Tests, Jump
ì Branch on Equal (if $1 == $2, goto dest)
ì Set on Less Than (if $2 < $3, set $1 = 1, otherwise 0)
ì Jump (goto dest)
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beq <reg1>, <reg2>, <destination>
slt <reg1>, <reg2>, <reg3>
j <destination>
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Task : Write Code
ì Write MIPS assembly for:
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if (A == B) { <equal-‐code> } else {
<not-‐equal-‐code> } <aker-‐if-‐code>
A==B?
… …
True False
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Task : Write Code
ì Write MIPS assembly:
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Code:
beq $s0,$s1,equal <not-equal-code> j done
equal: <equal-code> j done
done: <aker-‐if-‐code>
Map: $s0 = A $s1 = B
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Task : Write Code
ì Write MIPS assembly for:
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while (A != B) { <loop-‐body> } <post-‐loop-‐code>
A!=B?
…
…
True
False
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Task : Write Code
ì Write MIPS assembly:
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Code:
start: beq $s0,$s1,done <loop-body> j start
done: <post-loop-code>
Map: $s0 = A $s1 = B
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There are many, many, variaAons of branch or test instrucAons intended to simplify programming
1. Show: Appendix A Reference
2. Discuss: InstrucAon versus Pseudo-‐InstrucLon
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Resources
ì Resources on Website – view “Resources” page ì MIPS InstrucHon Set (parAal guide)
ì Resources available in Sakai site (under ECPE 170) ì HP_AppA.pdf
ì Appendix A from famous Hennessy & Pakerson Computer OrganizaLon textbook
ì Assemblers, Linkers, and the SPIM simulator ì StarAng on page 51 is an overview of the MIPS assembly
commands! ì MIPS_Green_Sheet.pdf
ì “Cheat sheet” for expert programmers ì MIPS commands, registers, memory convenAons, …
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ì MIPS Simulator Walkthrough
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