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Peter Asbeck
Lots of Watts and Plenty of MHz:An Overview of Power Amplifier
Research at UCSD
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Power Amplifier Faculty & Researchers
RF Integrated Circuit Group
Prof. Larry Larson
Prof. Gabriel RebeizApplied Electromagnetics Group
High Speed Device GroupProf. Peter Asbeck
Prof. James BuckwalterHigh Speed Integrated Circuits Group
Don KimballCal IT2
Center for Wireless Communications
California Insitute for Telecommunications& Information Technology
Center for WirelessCommunications
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Center for Wireless Communications
Center for WirelessCommunications
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Wireless systems
Advancement of Wireless Communications
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EfficiencyBandwidthIntegrability, low costMultiband, adaptivityLow noise / interference
Shannon limit R> receiver powerPA dissipation is critical
Perversity of amplifier circuitsPAR and bandwidth are the enemies of efficiency!
Critical Factors for Future Wireless Systems
Challenges for Power Amplifiers
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Agenda
Path to high efficiency & bandwidth in Base-station PAs
Handset PA development
Future technology opportunities
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Critical problem for power efficiency:Varying signal power level
Power/Pave (dB scale)
Prob
abili
ty~8 dB peak to average power ratio
Class AClass B
0
0.2
0.4
0.6
0.8
1
0 0.2 0.4 0.6 0.8 1
Effic
ienc
y
Average power
Class A
0
0.2
0.4
0.6
0.8
1
0 0.2 0.4 0.6 0.8 1Pout (normalized)
Maximum power
EER/ET
0.0%
1.0%
2.0%
3.0%
4.0%
5.0%
-60 -50 -40 -30 -20 -10 0 10 20 30
P out (dBm)
Prob
abili
ty
Power Control Variation
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Envelope Tracking (ET) Technique
Envelope Amplifier provides dynamic drain voltageMaximizes PA efficiency by keeping RF transistor
closer to saturation for all envelope amplitudes
EnvelopeAmplifier
Dynamic Drain VoltageDCSupply
RFSignal Out
Volta
ge
Time
RFSignal
In
RFAmplifier
EnvelopeDetector
Drain voltage tracks envelope
of RF signal
In Envelope Tracking, PA is quasi-linear.Input signal contains envelope and phase information.
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Pout (dBm)
Effic
ienc
y
Vcc1Vcc2
Vcc3 Vcc4 Vcc5
ET System Maximizes Efficiency Vs Power By Adjusting Output Bias (Vcc or Vdd)
Schematic Dependence of Efficiency on Output Power
EfficiencyFor ET system
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DAC
DC/DC
Drivers
DC
UpconDAC
Drain Modulator
WCDMA
RFOutput
Envelope
PAFinal stage
ET/E
ER a
ndPr
edis
tort
ion
DSPI
Q
DownconADC
Experimental Envelope Tracking Amplifier
High PowerRF Stage
F= 2.1 GHz
Complex system includingRF stage, analog/digital dynamic power supply, digital predistortion, up and down-converters
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X1=0
Harmonic Load TuningSimulated Efficiency vs Harmonic Load Reactance
Class F-1Class F-1
Class FClass F
Class B
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Envelope Amplifier Design
EnvelopeSignal
CurrentSense
RF Power Transistor Drain Bias
LinearStage
VDC
SwitcherStage
Voltage SourceHigh BWEff = 50%
Current SourceLow BW
Eff > 90%
Envelope Amplifier: Overall Efficiency >70%BW = 50 MHz
VDC
Kimball
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Signal generation Switcher controlTime alignment
DSP
EnvelopeSignal
CurrentSense
RF Power Transistor Drain/Collector Bias
LinearStage
VDC
Switcher
Voltage SourceHigh BW
Current SourceLow BW
VDC
iL1iLN iRVR
Vsw1VS
L1D1 isw1
Main Switcher VDC Current SourceMedium BW
iL2
Vsw2
L2 D2
isw2
L2 < L1
Aux
DSP-driven Main switcher provides high slew rate currentAux switcher compensates DC error between Linear stage and Main switcher
Improved Envelope Amplifier Design
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[dBc] ACPR1 ACPR2 NRMSEBefore DPD -35.4 -45.5 6.8%
After ML DPD -45.3 -50.7 2.4%After Memory
mitigation-55.5 -60.2 0.7%
ET PA with Dual Switcher / HVHBT PA
PDF
CE Gain PAE RF PA Envelope Amplifier
65.6% 12.3dB 61.7% 82% 80%
WCDMA6.6 dB PAPR
Before DPD
After DPD
After Memory Mitigation*
Record
Efficiency
Probability
Pout=67W
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ET System: Path to Wider Bandwidth
EnvelopeAmplifier
DCSupply
RF Signal Out
Amplitude
RFPowerAmplifierRF Signal In
(WiMAX, 3GPP LTE)
Enough Bandwidth
Trade-off
Efficiency vs BandwidthDoesnt need to be exact replica of input envelope as long as it does not clip output envelope
Vdd
New envelope: Power spectrumNew envelope: time domain
time frequency
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Mark-II PA Digital Predistortion Testbench100 MHz Instantaneous BandwidthTunable Carrier: 100 MHz to 4.0 GHz
Can be extended to mm-waves using additional up/down converters
210 MSamples/s 14-bits DACs & ADCs52 MHz Digital IF (no I/Q impairments)Up to 220 data vectors (5-ms sequence length)
Can operate in EER, ET, or linear mode
Memory effect compensation available
Fully coded in Matlab, to allow development of new DPD algorithms
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Digital Correction of Amplifier Output
|Vout| vs |Vin|
No correction Memoryless correctionFull correction(with memory effect)
Measurements for commercial WLAN amplifier
Nonlinearity and "memory effect" must be mitigated in order to achieve signal accuracy needed for complex signal constellations
Input voltage (normalized) Input voltage (normalized) Input voltage (normalized)
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AgendaPath to high efficiency & bandwidth in Base-station PAs
Handset PA development How to make a CMOS PAHow to make a mostly digital PA
Future technology opportunities
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Stacked-FET Structure
0.2 0.4 0.6 0.80.0 1.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
4.0
time, nsec
Vgs
1, V
Vds
1, V
Vgs
2V
ds2
Vgs
3V
ds3
Vds, i
Vgs, i
Vds and Vgs swing of each FET
All FETs are operating in the safe region
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34-dBm 4-Stacked PA in SOI CMOS
0.28-m SOI CMOS process(S T Microelectronics)
Total device width = 5 mm x (4 devices) Chip size (include pads) = 0.43 x 1.56 mm2
Rload=11 ohms
In
RL
VG4
VG3
VDD
VG2
VG1
Cm1
Cm2
C2
C3
C4
m1
m2
m3
m4
Cm3
Cm4
Cm5
Cf
Rf
TL1TL2
TL3TL4
TL5
TL6
TL7TL8In
RL
VG4
VG3
VDD
VG2
VG1
Cm1
Cm2
C2
C3
C4
m1
m2
m3
m4
Cm3
Cm4
Cm5
Cf
Rf
TL1TL2
TL3TL4
TL5
TL6
TL7TL8
In InIn In
OutOutOutOut GND
GNDGNDGNDGNDGND
GNDGNDGNDGND
VG2
VG4
VG3
GND
Gate capacitors
CWC Project withS T Micro
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4-Stacked CMOS PA Performance with 1.9GHz WCDMA signal
High powerGood efficiencyGood linearity
Meets spec (-33dBc ACLR1)29.4 dBm output powerPAE=41.4 %
Comparable to GaAs HBT PAs
VDD=6.5V
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On-Going Research in CMOS Envelope Amplifierfor LTE Handset Applications
Linear Stage
Switching Stage
Sense & Control
A combined class-AB and switch-mode regulator based supply modulator with a master-slave architecture is used to achieve wide bandwidth and high efficiency
Anti-shoot Through &
Gate Drivers
M6
V DD
L
M1
M2
M4
M3
OTA
Env_in
To PA
Rsen
M5
OP AMP
c
idia
R2R1
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RL
Q1 Q2
Q3
Q4
BuckConverterw/ PWM
SwitchedResonator
(res)PM
AM
DSP
Digital Envelope-Tracking CMOS Handset Switching Mode Power Amplifier
Multi-mode, Multi-band
Digital PA Techniques- RF pulse modulation- Unit-cell switching- Charge sampling regulator 0.01
0.1
1
10
100
-10 0 10 20 30 40
Output Power (dBm)
Tota
l Effi
cien
cy (%
)All Cell, PWM1/10 Cell, PWM1/10 Cell, CMReference
15dB back-off
x2.4
850MHz
1.9 1.91 1.92 1.93 1.94 1.95 1.96 1.97 1.98 1.99 2-110
-100
-90
-80
-70
-60
-50
-40
-30
Frequency (GHz)
Pow
er/fr
eque
ncy
(dB
/Hz)
Slew ImpairmentNo Phase CorrectionSlew ImpairmentPhase PDM CorrectionNo Slew ImpairmentNo Phase Correction
1.9 1.91 1.92 1.93 1.94 1.95 1.96 1.97 1.98 1.99 2-110
-100
-90
-80
-70
-60
-50
-40
-30
Frequency (GHz)
Pow
er/fr
eque
ncy
(dB
/Hz)
Slew ImpairmentNo Phase CorrectionSlew ImpairmentPhase PDM CorrectionNo Slew ImpairmentNo Phase Correction
Slew ImpairmentNo Phase CorrectionSlew ImpairmentPhase PDM CorrectionNo Slew ImpairmentNo Phase CorrectionACPR improve
CWC Project with Panasonic
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Bin.-to-Therm. Decoder
Amplitude Control Word
TunableMatchingCircuit
Vdd
ModulatedSignal
Phase-modulatedSignal
127 Unit Cells
3 Binary Cells
1 x
1 x
1 x
1/2 x
1/8 x
DPA core
Decoder
Decoder
Input Output
0
10
20
30
40
50
60
70
80
-20 -10 0 10 20 30
Output Power [dBm]
Pout
/Pdc
[%]
Vdd = 2.1 V, throughVdd = 1.5 V, throughVdd = 1.0 V, throughVdd = 0.5 V, throughVdd = 2.1 V, input attenuationVdd = 1.5 V, input attenuationVdd = 1.0 V, input attenuationVdd = 0.5 V, input attenuation
Digitally-Modulated CMOS PAPower controlled by number of "on" transistors
CWC Project with S T Micro
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DPD Application to Skyworks GaAs HBT WCDMA PA Module
4mm x 4mm handset PA module, experimental variant of SKY77174 optimized for operation at 1.95GHz
Features high linearity (better than 40 dB ACPR) up to 29 dBm in WCDMA mode
WCDMA3.3 dB PAPR20 6 dBm1.95 GHz
50 load(nominal)
Currentreading
Interstagematch
Outputmatch
bias and gain control
DA PA
3.4 V(nominal)
Module
Inputmatch
MMIC
|Vo,sat|
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WCDMA Performance Using Digital PredistortionPerformance at high power
Average power consumption assuming CDMA power usage profiles
Hig
h Po
wer
Pe
rfor
man
ceAv
erag
e Pe
rfor
man
ce 371
189
454
269
0
100
200
300
400
500
600
Original PA Module Retuned PA w/ DPDAve
rage
Pow
er C
onsu
mpt
ion
(mW
)
UrbanSub-urban
Power Savings ~ 180mW
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Agenda
Path to high efficiency & bandwidth in Base-station PAs
Handset PA development
Future technology opportunitiesAdaptive PAsBroadband PAsHigh frequency PAs
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n-GaN layerTi/Au/Pd/Au
n+GaN layer
c-Sapphire
InGaN layer GaN cap layer
Ni contact
GaN buffer layer
-+
Wm
ax
W
High Q High Voltage Varactors for Adaptive PAs
GaN is 40x better than Si for high voltage varactor
UCSD Varactor ObjectivesHigh voltage (>100V)Low Rseries=> High Q for basestations (>150)& design for high linearity
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GaN Single-Chip Broadband Amplifier
Simulated Drain Eff.
Measured Drain Eff.
Simulated PoutMeasured Pout
Ranges from 41 dBm to 41.7 dBm
Ranges from 54.4% to 76.6%
C1C1RF
CF
Stack GaN for higher Zout, higher power>12W out single chip!Efficiency ~60% 400MHz to 1.8GHz
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What's Coming in GaN: On-going Research in Scaled Devices
HRL Laboratories
Lg=40nmFmax=400GHz
BV~42V
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Quartz antenna bonded
on a SiGe chip
DigitalPredistorter DAC
Upconverter
downconverterADCVinMemVoutMem
DSPAdaptation
LUTDig
ital
Bas
eban
d M
odul
ator
Dat
a in am
plifier/antenna array
Signal Generator
DSP
SiGe HBT &45nm CMOS SOI
UCSD mm-Wave Power Amplifier Arrays
Program goals: 4W at 45GHz1W at 94 GHz0.25W at 138GHz
All Si technology
40-60% efficiency
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Measured 33 W-Band Power Amplifier
Quartzedge
RF Input
EIRP > 34 dBm at 90 99 GHz (@ 2.0 V)
Array can be scaled to entire wafer, achieving EIRP in the MW rangeScanning phased arrays possible with incremental modifications
Dramatic increase in radiated power density
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SummaryUCSD has a wide variety of projects for handset and basestation PAs
multiple technologies, frequencies & power levelsCMOS / HBT / GaN
UCSD has expertise in Digital Predistortion Techniquesalong with state-of-the-art test benches
State-of-art research is on-going in Envelope Tracking for both Basestation and Handset PAs
=> critical to the future of high performance PAsfor signals with high PAR (eg LTE!)
Hear more details at this afternoon's sessions!
Slide Number 1Slide Number 2Slide Number 3Slide Number 4Slide Number 5Slide Number 6Slide Number 7Envelope Tracking (ET) TechniqueSlide Number 9Slide Number 10Slide Number 11Slide Number 12Slide Number 13Slide Number 14ET System: Path to Wider BandwidthMark-II PA Digital Predistortion TestbenchSlide Number 17Slide Number 18Slide Number 19Slide Number 20Slide Number 21Slide Number 22Digital Envelope-Tracking CMOS Handset Switching Mode Power AmplifierMulti-mode, Multi-bandSlide Number 24Slide Number 25WCDMA Performance Using Digital PredistortionSlide Number 27Slide Number 28Slide Number 29Slide Number 30Slide Number 31Slide Number 32Slide Number 33