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Lecture 14: Wires
![Page 2: Lecture 14: Wires - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect14.pdf · 14: Wires CMOS VLSI DesignCMOS VLSI Design 4th Ed. 5 Layer Stack AMI 0.6 μm process has](https://reader030.vdocuments.mx/reader030/viewer/2022040919/5e952e623ae22234de6e2063/html5/thumbnails/2.jpg)
14: Wires 2CMOS VLSI DesignCMOS VLSI Design 4th Ed.
OutlineIntroductionInterconnect Modeling– Wire Resistance– Wire Capacitance
Wire RC DelayCrosstalkWire EngineeringRepeaters
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14: Wires 3CMOS VLSI DesignCMOS VLSI Design 4th Ed.
IntroductionChips are mostly made of wires called interconnect– In stick diagram, wires set size– Transistors are little things under the wires– Many layers of wires
Wires are as important as transistors– Speed– Power– Noise
Alternating layers run orthogonally
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14: Wires 4CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Wire GeometryPitch = w + sAspect ratio: AR = t/w– Old processes had AR << 1– Modern processes have AR ≈ 2
• Pack in many skinny wires
l
w s
t
h
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14: Wires 5CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Layer StackAMI 0.6 μm process has 3 metal layers– M1 for within-cell routing– M2 for vertical routing between cells– M3 for horizontal routing between cells
Modern processes use 6-10+ metal layers– M1: thin, narrow (< 3λ)
• High density cells– Mid layers
• Thicker and wider, (density vs. speed)– Top layers: thickest
• For VDD, GND, clk
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14: Wires 6CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Example
Intel 90 nm Stack Intel 45 nm Stack[Thompson02] [Moon08]
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14: Wires 7CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Interconnect ModelingCurrent in a wire is analogous to current in a pipe– Resistance: narrow size impedes flow– Capacitance: trough under the leaky pipe must fill first – Inductance: paddle wheel inertia opposes changes in flow rate
• Negligible for mostwires
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14: Wires 8CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Lumped Element ModelsWires are a distributed system– Approximate with lumped element models
3-segment π-model is accurate to 3% in simulationL-model needs 100 segments for same accuracy!Use single segment π-model for Elmore delay
C
R
C/N
R/N
C/N
R/N
C/N
R/N
C/N
R/N
R
C
L-model
R
C/2 C/2
R/2 R/2
C
N segments
π-model T-model
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14: Wires 9CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Wire Resistanceρ = resistivity (Ω*m)
R = sheet resistance (Ω/ )– is a dimensionless unit(!)
Count number of squares– R = R * (# of squares)
l
w
t
1 Rectangular BlockR = R (L/W) Ω
4 Rectangular BlocksR = R (2L/2W) Ω = R (L/W) Ω
t
l
w w
l
l lR Rt w wρ
= =
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14: Wires 10CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Choice of MetalsUntil 180 nm generation, most wires were aluminumContemporary processes normally use copper– Cu atoms diffuse into silicon and damage FETs– Must be surrounded by a diffusion barrier
43.0Titanium (Ti)5.3Tungsten (W)2.8Aluminum (Al)2.2Gold (Au)1.7Copper (Cu)1.6Silver (Ag)Bulk resistivity (μΩ • cm)Metal
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14: Wires 11CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Contacts ResistanceContacts and vias also have 2-20 ΩUse many contacts for lower R– Many small contacts for current crowding around
periphery
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14: Wires 12CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Copper IssuesCopper wires diffusion barrier has high resistanceCopper is also prone to dishing during polishingEffective resistance is higher
( ) ( )dish barrier barrier2lR
t t t w tρ
=− − −
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14: Wires 13CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Example
Compute the sheet resistance of a 0.22 μm thick Cu wire in a 65 nm process. Ignore dishing.
Find the total resistance if the wire is 0.125 μm wide and 1 mm long. Ignore the barrier layer.
8
6
2.2 10 Ω m 0.10 /0.22 10 m
R−
−
×= = Ω
×i
( ) 1000 m0.10 Ω/ 800 0.125 m
R μμ
= = Ω
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14: Wires 14CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Wire CapacitanceWire has capacitance per unit length– To neighbors– To layers above and below
Ctotal = Ctop + Cbot + 2Cadj
layer n+1
layer n
layer n-1
Cadj
Ctop
Cbot
ws
t
h1
h2
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14: Wires 15CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Capacitance TrendsParallel plate equation: C = εoxA/d– Wires are not parallel plates, but obey trends– Increasing area (W, t) increases capacitance– Increasing distance (s, h) decreases capacitance
Dielectric constant– εox = kε0
• ε0 = 8.85 x 10-14 F/cm• k = 3.9 for SiO2
Processes are starting to use low-k dielectrics– k ≈ 3 (or less) as dielectrics use air pockets
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14: Wires 16CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Capacitance FormulaCapacitance of a line without neighbors can be approximated as
This empirical formula is accurate to 6% for AR < 3.3
0.25 0.5
ox 0.77 1.06 1.06totw w tC lh h h
ε⎡ ⎤⎛ ⎞ ⎛ ⎞= + + +⎢ ⎥⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠⎢ ⎥⎣ ⎦
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14: Wires 17CMOS VLSI DesignCMOS VLSI Design 4th Ed.
M2 Capacitance DataTypical dense wires have ~ 0.2 fF/μm– Compare to 1-2 fF/μm for gate capacitance
0
50
100
150
200
250
300
350
400
0 500 1000 1500 2000
Cto
tal (
aF/μ
m)
w (nm)
Isolated
M1, M3 planes
s = 320s = 480s = 640s= 8
s = 320s = 480s = 640
s= 8
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14: Wires 18CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Diffusion & PolysiliconDiffusion capacitance is very high (1-2 fF/μm)– Comparable to gate capacitance– Diffusion also has high resistance– Avoid using diffusion runners for wires!
Polysilicon has lower C but high R– Use for transistor gates– Occasionally for very short wires between gates
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14: Wires 19CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Wire RC DelayEstimate the delay of a 10x inverter driving a 2x inverter at the end of the 1 mm wire. Assume wire capacitance is 0.2 fF/μm and that a unit-sized inverter has R = 10 KΩ and C = 0.1 fF.
– tpd = (1000 Ω)(100 fF) + (1000 + 800 Ω)(100 + 0.6 fF) = 281 ps
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14: Wires 20CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Wire EnergyEstimate the energy per unit length to send a bit of information (one rising and one falling transition) in a CMOS process.
E = (0.2 pF/mm)(1.0 V)2 = 0.2 pJ/bit/mm= 0.2 mW/Gbps
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14: Wires 21CMOS VLSI DesignCMOS VLSI Design 4th Ed.
CrosstalkA capacitor does not like to change its voltage instantaneously.A wire has high capacitance to its neighbor.– When the neighbor switches from 1-> 0 or 0->1,
the wire tends to switch too.– Called capacitive coupling or crosstalk.
Crosstalk effects– Noise on nonswitching wires– Increased delay on switching wires
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14: Wires 22CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Crosstalk DelayAssume layers above and below on average are quiet– Second terminal of capacitor can be ignored– Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors– Miller effect A B
CadjCgnd Cgnd
2Cgnd + 2 Cadj2VDDSwitching opposite A0Cgnd0Switching with A1Cgnd + CadjVDDConstantMCFCeff(A)ΔVB
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14: Wires 23CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Crosstalk NoiseCrosstalk causes noise on nonswitching wiresIf victim is floating:– model as capacitive voltage divider
Cadj
Cgnd-v
Aggressor
Victim
ΔVaggressor
ΔVvictim
adjvictim aggressor
gnd v adj
CV V
C C−
Δ = Δ+
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14: Wires 24CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Driven VictimsUsually victim is driven by a gate that fights noise– Noise depends on relative resistances– Victim driver is in linear region, agg. in saturation– If sizes are same, Raggressor = 2-4 x Rvictim
11
adjvictim aggressor
gnd v adj
CV V
C C k−
Δ = Δ+ +
( )( )
aggressor gnd a adjaggressor
victim victim gnd v adj
R C Ck
R C Cττ
−
−
+= =
+
Cadj
Cgnd-v
Aggressor
Victim
ΔVaggressor
ΔVvictim
Raggressor
Rvictim
Cgnd-a
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14: Wires 25CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Coupling WaveformsSimulated coupling for Cadj = Cvictim
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14: Wires 26CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Noise ImplicationsSo what if we have noise?If the noise is less than the noise margin, nothing happensStatic CMOS logic will eventually settle to correct output even if disturbed by large noise spikes– But glitches cause extra delay– Also cause extra power from false transitions
Dynamic logic never recovers from glitchesMemories and other sensitive circuits also can produce the wrong answer
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14: Wires 27CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Wire EngineeringGoal: achieve delay, area, power goals with acceptable noiseDegrees of freedom:– Width – Spacing– Layer– Shielding
Del
ay (n
s): R
C/2
Wire Spacing(nm)
Cou
plin
g: 2C
adj /
(2C
adj+C
gnd)
00.20.40.6
0.81.01.21.4
1.61.82.0
0 500 1000 1500 20000
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 500 1000 1500 2000
320480640
Pitch (nm)Pitch (nm)
vdd a0a1gnd a2vdd b0 a1 a2 b2vdd a0 a1 gnd a2 a3 vdd gnd a0 b1
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14: Wires 28CMOS VLSI DesignCMOS VLSI Design 4th Ed.
RepeatersR and C are proportional to lRC delay is proportional to l2
– Unacceptably great for long wiresBreak long wires into N shorter segments– Drive each one with an inverter or buffer
Wire Length: l
Driver Receiver
l/N
Driver
Segment
Repeater
l/N
Repeater
l/N
ReceiverRepeater
N Segments
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14: Wires 29CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Repeater DesignHow many repeaters should we use?How large should each one be?Equivalent Circuit– Wire length l/N
• Wire Capacitance Cw*l/N, Resistance Rw*l/N– Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W
R/W C'WCwl/2N Cwl/2N
RwlN
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14: Wires 30CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Repeater ResultsWrite equation for Elmore Delay– Differentiate with respect to W and N– Set equal to 0, solve
2
w w
l RCN R C
′=
( )2 2pdw w
tRC R C
l′= +
w
w
RCWR C
=′
~40 ps/mm
in 65 nm process
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14: Wires 31CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Repeater EnergyEnergy / length ≈ 1.87CwVDD
2
– 87% premium over unrepeated wires– The extra power is consumed in the large
repeatersIf the repeaters are downsized for minimum EDP:– Energy premium is only 30%– Delay increases by 14% from min delay