Download - Lec1 Intro Low Power Design
Introduction to Low Power Design
M. Balakrishnan
CSE Department, IIT Delhi
CSV881: Selected Topics in Hardware Design(Low Power Design)
1-credit course (14 lectures)Instructors:
Prof. M. Balakrishnan (CSE Department) Dr. Preeti Ranjan Panda (CSE Department)
Classes Bala’s classes: Monday 4:00 to 5:00 PM Preeti’s classes: Wednesday 3:00 to 4:00 PM
Live classes at IITD and Cadence NOIDA through 2-way audio-video link
Class ScheduleS.No. Topics Faculty Time Dates
1 Introduction to Low Power Design M. Balakrishnan 4 - 5 PM 15-Sep
2 Low Power RTL Synthesis M. Balakrishnan 4 - 5 PM 22-Sep
3 Power Optimisations in Processor Architectures M. Balakrishnan 4 - 5 PM 29-Sep
4 Low Power Logic Design Preeti Ranjan Panda 3 - 4 PM 1-Oct
5 Low Power Logic Synthesis Preeti Ranjan Panda 3 - 4 PM 8-Oct
6 Power Optimisations in Processor Architectures M. Balakrishnan 4 -5 PM 13-Oct
7 Power Aware Program Transformations M. Balakarishnan 4 - 5 PM 20-Oct
8 Low Power FSM Synthesis Preeti Ranjan Panda 3 - 4 PM 22-Oct
9 Power Issues in Memory Systems Preeti Ranjan Panda 3 - 4 PM 29-Oct
10 Power Aware Program Transformations M. Balakarishnan 4 - 5 PM 3-Nov
11 Power Issues in Bus Design Preeti Ranjan Panda 3 - 4 PM 5-Nov
12 Power Estimation & Modeling M. Balakrishnan 4 - 5 PM 10-Nov
13 Power Issues in OS Preeti Ranjan Panda 3 - 4 PM 12-Nov
14 Power Issues in OS Preeti Ranjan Panda 3 - 4 PM 19-Nov
Know Your Instructors
M. Balakrishnan Preeti Ranjan Panda
Course Evaluation
Credit Registration– Transcribe one lecture (deadline: 2 weeks
from the lecture date) – 50%– 1 hour test at the end of the course – 50%
Audit/Professional Candidate Registration– 1 hour test at the end of the course – 50%
(For satisfactory grade minimum 50% marks)
Motivation for Low Power Design
Low power design is important from three different reasons
• Device temperature– Failure rate, Cooling and packaging costs
• Life of the battery– Meantime between charging, System cost
• Environment – Overall energy consumption
Power Projections (2000)
40048008
8080
8085
8086
286 386 486Pentium®
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Pow
er
Den
sit
y (
W/c
m2)
Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Sun’s
Surface
Source: Borkar De, Intel©
Power Projections (2000)
5KW 18KW
1.5KW 500W
40048008
80808085
8086286
386486
Pentium®
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
Pow
er
(Watt
s)
P6
transition from NMOS to CMOS
Source: Borkar De, Intel©
Low Power or Low Energy Design
• Power – Direct impact on instantaneous energy
consumption and temperature
• Energy – Power integrated over time is energy and
impact on battery shelf life and environment
E(T) = ∫ P(t) dt0
T
Power Consumption
• Dynamic– Transition – Short circuit
• Leakage– Sub-threshold leakage– Diode/Drain leakage– Gate leakageAt 250nm leakage power was only 5% but it is increasing rapidly as geometries decrease
Dynamic Energy Consumption
Energy/transition = CL * VDD2 * P01
Power = CL * VDD2 * f
Vin Vout
CL
VddTransition Power
Dynamic Energy Consumption
Energy/transition = tsc * VDD * Ipeak * P 0/11/0
Power = tsc * VDD * Ipeak * f
Vin Vout
CL
VddShort-circuit Power
Leakage Energy
Vout
Independent of switching
Sub-threshold current
Drain junction leakageOFF
Gate leakage
Dynamic vs Static Power
0.01 0.1 1 10
Gate Length (microns)
1E-8
1E-6
1E-4
1E-2
1E+0
1E+2
1E+4
Po
we
r D
en
sit
y (
W/c
m^
2)
Shrinking Margin
SubThresholdPower
Active Power
Source: Leon Stok, DAC 42©
Low Power Design Needs
• Low power design techniques– Effectiveness– Effect/tradeoff with other design parameters
like area (cost), performance, reliability, manufacturability etc.
• Power modeling and estimation– Accuracy of the models– Time for estimation
Design Approaches
• System design: Top down– Effective low power transformations in
synthesis– Fast estimation techniques for an effective
exploration of a large design space
• Cell library design: Bottom up– Low power circuit design techniques– Accurate estimation – Effective models for synthesis tools
Design Levels
• System
• Algorithmic/Module
• RTL
• Gate
• Circuit
• Device technology
System Level DesignSame MP3 Application running on different systems consume significantly different amounts of power
• System partitioning
• Busses/Memory/IO devices /interfaces
• Choice of components
• Coding
• System states (sleep/snooze etc)
• DVS/DFS/..
Algorithmic/sub-system Level
• Choice of algorithm (operation count etc.)
• Word length choices
• Module interfaces
• Implementation technology– SW: Processor selection– HW: ASIC/FPGA/..
• Behavioral synthesis constraints and trade-off
RTL
• Pipelining/retiming
• Module selection
• Multiple frequency and voltage islands
• Reduction in switching activity through transformations
Gate Level
• Clock gating
• Power gating
• Clock tree optimization
• Logic level transformations to reduce switching activity
Circuit Level
• Transistor sizing
• Power efficient circuits
• Cell design
• Multi-threshold circuits
Device Technology
• Multi-oxide devices
• Multiple “cell types” on a single substrate– Logic, SRAM, Flash etc.
• Support for many other low power design techniques (multiple thresholds, multiple voltages, multiple frequencies etc.)
References
Thank You