Download - Ip so c-30sept2010
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Challenges in Designing a Low Power Speech Processing SoC
-a designer’s perspective
S. Krishnakumar Rao C-DAC
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2C-DAC/TVM/HDG/Sep-10
Agenda
About C-DAC Why low power? Technology and Process selection Low Power Design techniques Speech processor SoC ASTRA portfolio of IP
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3C-DAC/TVM/HDG/Sep-10
About C-DAC
Scientific Society under DIT, Govt. of India Application oriented R&D in Electronics and IT Eleven development centres across India
Technologies High Performance Computing Professional Electronics Health Informatics Ubiquitous Computing Education and Training
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4C-DAC/TVM/HDG/Sep-10
C-DAC, Thiruvananthapuram
VLSI Design Broadcast and Communication Power Electronics Control and Instrumentation Strategic Electronics Cyber Security Language Technologies
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5C-DAC/TVM/HDG/Sep-10
VLSI Design Group at C-DAC(T)
Professional design services with a well developed infrastructure for customers to realize their ideas from concept-to-silicon and to product; competitively
Design & development of IP cores for semiconductors, in the processor, serial communication and bus interfacing area under the brand name ASTRA
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6C-DAC/TVM/HDG/Sep-10
Why Low Power?
Limited Battery Capacity
For Minimal Heat Dissipation Heat Sink, System Size/Weight/Cost
For Chip/System reliability
Save Energy
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7C-DAC/TVM/HDG/Sep-10
Low Power Design - Application areas
Bio-Medical Mobile Military Space
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8C-DAC/TVM/HDG/Sep-10
Constraints in ASIC design
The main constraints are
Speed/Performance Power Area Cost (EDA, IP, NRE, Manpower..)
Primary constraints should be identified and prioritized for Technology & Process selection IP selection Design methodology
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9C-DAC/TVM/HDG/Sep-10
Technology & Process selection
Criteria for selection Operating voltage Operating frequency Power dissipation Chip area Cost of production Yield
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10C-DAC/TVM/HDG/Sep-10
Technology & Process: for Low Power Operating Voltage
Choose the technology based on operating voltage
Minimise power converters
Power consumption
Choose low leakage (HVT) cells for low frequency application
When frequency of operation increases LVT cells can be used to optimize critical paths
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11C-DAC/TVM/HDG/Sep-10
Technology & Process: for Low Power Dynamic power reduces with technology scaling,
but leakage power increases
Development and fabrication cost increases with technology scaling
Availability of low power IP such as RAM, ROM & NVM
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12C-DAC/TVM/HDG/Sep-10
Selection of Hard IP: RAM & ROM
Power consumption Macros with low standby current Power consumption can be reduced by efficient
usage Cost
Free IP available from vendors, if cost is of prime concern
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13C-DAC/TVM/HDG/Sep-10
Selection of Hard IP: NVM
Require multiple voltage for operation
Design techniques can be adopted to reduce the power consumption of NVM
The NVM content can be copied and executed from the RAM and enabling the standby mode for NVM thereafter.
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14C-DAC/TVM/HDG/Sep-10
Selection of Hard IP : NVM
Cost perspective: License fee Use available memory IP and avoid cost escalation for
customisation Evaluate options depending on IP availability and cost
An MTP can be replaced with an OTP using an efficient Memory management algorithm.
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15C-DAC/TVM/HDG/Sep-10
Selection of Hard IP: Clock
management PLL Advantages
Variable clock frequency Highly stable clock with low jitter
Disadvantage Power consumption
Oscillator Pad Advantage
Less power consumption Disadvantage
Single frequency
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16C-DAC/TVM/HDG/Sep-10
Low Power Design techniques
Industry has a bunch of low power design techniques. But are they all required for my design?
Select the design techniques wisely?
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17C-DAC/TVM/HDG/Sep-10
Low Power Design techniques
Clock gating Data gating Power gating Frequency scaling Voltage scaling Variable device threshold
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18C-DAC/TVM/HDG/Sep-10
Clock gating
CLK
EN
EN1
GCLK
EN
D Q
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19C-DAC/TVM/HDG/Sep-10
Clock gating Dynamic power reduction Define the Active mode of the chip Identify switching activity of various modules Apply clock gating efficiently Disadvantages
Area overhead CG without proper analysis may result in higher
power consumption for certain modules
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20C-DAC/TVM/HDG/Sep-10
Data Gating
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21C-DAC/TVM/HDG/Sep-10
Data Gating
Dynamic power reduction If not used efficiently Data gating will cause
More power consumption Area overhead Critical path violation
Switching activity of candidates to be analyzed prior to gating
Usually more effective for power reduction in bus-structures
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22C-DAC/TVM/HDG/Sep-10
Power gating
Courtesy: Cadence Design Systems
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23C-DAC/TVM/HDG/Sep-10
Power gating Advantage
Leakage power reduction
Disadvantages Design complexity Verification complexity increases
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24C-DAC/TVM/HDG/Sep-10
Voltage and Frequency scaling
Voltage & frequency scaling are done in tandem
Courtesy: Cadence Design Systems
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25C-DAC/TVM/HDG/Sep-10
Speech Processor Application
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26C-DAC/TVM/HDG/Sep-10
NAADA - Speech processor SoC for low power speech processing applications Integrates in-house IP Features
1.2V single supply operation Low power consumption < 5mW Frequency of operation - 20MHz Integrated 1Mbit NVM 64KB RAM 32KB ROM
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27C-DAC/TVM/HDG/Sep-10
“NAADA” integrates
OTP128KB
1.2V
ROM32KB1.2V
SRAM64KB1.2V
DSP Engine
CPU
Glue Logic Standard Cells
(1.2V, 130nm,LL)
DSP Engine
Volt. Doubler
In-house IPs Integrated
32-bit RISC processor DSP IPs
FFT & IFFT MAC
UART SPI
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28C-DAC/TVM/HDG/Sep-10
ASTRA – IP Portfolio
Processor ER8051: 8-bit microcontroller compatible with Intel 8051 ER8085: 8-bit microprocessor compatible with Intel 8085 ER9101: 16-bit Bit Slice ALU ER902: 32-bit RISC Processor ERASP8051: Asynchronous 8-bit microcontroller
Peripheral ERRTC: Real Time Clock ERTIMER: 32-bit configurable timer ERDMA: 8237 compatible DMA controller ER15530: Manchester Encoder Decoder
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29C-DAC/TVM/HDG/Sep-10
ASTRA – IP Portfolio Communication
ER16450: UART compatible with NS16450 ERUSB2: USB 2.0 Device Controller ERMAC: IEEE802.3 compliant 100Mbps Media Access
Controller ERGMAC: IEEE802.3 compliant 1Gbps Media Access Controller EROTG: USB2.0 On-The-Go Controller ERUSB2: USB2.0 Device Controller ERUSBHC: USB2.0 Host Controller ERSATAII: SATAII Host Controller ERPCIe: PCIe endpoint
Sigma-Delta ADC Mixed Signal IP
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30C-DAC/TVM/HDG/Sep-10
Thank You