Download - How Does Scan Work
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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
CombinationalLogic
X
X
X
CombinationalLogic
X
X
X
X
X
X
CombinationalLogic
CombinationalLogic
ScanEnable=1
PrimaryOutputs(PO)
PrimaryInputs(PI)
ScanOut
Scan
In
100101011
Thefirstthingweshoulddoistoputthescanflipflopsintoscanmode.WedothisbyusingtheScanEnablesignal.Inthiscase,forcingScan
Enableto1enablesthescanmode.
Notethatinitiallyallthescanflopsatunknownstate(X). Forindustrialcircuits,therearearchitecturalwaystoinitializeallflipflopstoknown
statesifneeded.
However,
for
this
particular
case,
assume
that
all
scan
flops
were
initially
at
unknown
state
X.
Wewanttoscaninthefollowingvector:100101011
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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
Combin
ationalLogic
0
1
1
CombinationalLogic
X
X
X
X
X
XCombin
ationalLogic
Combin
ationalLogic
ScanEnable=1
PrimaryOutputs(PO)
PrimaryInputs(PI)
ScanOut
Scan
In
100101
Andwestartscanninginthetestvectorwewanttoapply.Inthefigureabove,youseethatthefirst3bitsarescannedin.Weshiftinasinglebit
ateachclockcycle.Usually,thescanshiftfrequencyisveryslow,muchlowerthanthefunctionalfrequencyofthecircuit.Thisfrequencyis
currentlyabout100MHzformostASICcircuits.AMDuses400MHzshiftfrequency,whichisaprettyhighvalueforthatpurpose.Ofcourse,the
higherthetestfrequency,theshorterthetesttime.
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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
Combin
ationalLogic
PrimaryInputs(PI)
Scan
In
PrimaryOutputs(PO)
1
0
0
CombinationalLogic
0
1
1
1
0
1
Combin
ationalLogic
Combin
ationalLogic
ScanEnable=0
ScanOut
Atthispoint,wehaveshiftedinthecompletetestvector'100101011'.Wearedonewithshiftingin.WewilldisablescanmodebyforcingScan
Enableto0.
Notethattheshiftedintestvectoriscurrentlyappliedtothecombinationallogicpiecesthataredrivenbyscanflipflops.Itmeansthat2nd,
3rd,and
4th
combinational
logic
blocks
are
already
forced
test
inputs.
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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
Combin
ationalLogic
1
1
1
0
1
1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
CombinationalLogic
1
1
1
0
1
1
1
0
1
Combin
ationalLogic
Combin
ationalLogic
ScanEnable=0
PrimaryOutputs(PO)
PrimaryInputs(PI)
ScanOut
Scan
In
Thenextstepistoforceprimaryinput(PI)valuesandmeasuretheprimaryoutput(PO)values:force_PIandmeasure_PO.
Notethatfromthepreviousstep,theshiftedintestvectorwasalreadyappliedtothecombinationallogicpiecesthataredrivenbyscanflip
flops.Itmeansthat2nd,3rd,and4thcombinationallogicblockswerealreadyforcedtestinputs.Now,thesecombinationallogicblockshave
generatedtheir
outputs.
SinceweforcedvaluestoPI,the1stcombinationalblockalsohasitsoutputsready.Furthermore,theoutputsofthe4thcombinationalblockcan
nowbeobservedfromPOs.Wewillgettheoutputvaluesofcombinationalblock4bymeasuringPOs.
Fortherestofthecombinationalblocks(1,2,and3),weneedtopushtheoutputvaluesintoscanflipflopsandthenshiftthesevaluesout.
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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
Combin
ationalLogic
1
1
1
0
1
0
1
0
0
1
0
0
0
1
0
Combin
ationalLogic
CombinationalLogic
0
1
0
0
1
0
1
1
1
0
1
0
0
1
0
1
1
1Combin
ationalLogic
PrimaryOutputs(PO)
PrimaryInputs(PI)
Scan
In
ScanEnable=0
ScanOut
Inordertopushtheoutputvaluesofcombinationalblocks1,2,and3intoscanflipflops,wehavetotogglethesystemclock.Oncewetogglethe
systemclock,allDflipflops(scanflipflops)willcapturethevaluesattheirDinput.
Inthefigureabove,thecaptureeventisshown.
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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
Combin
ationalLogic
0
0
1
CombinationalLogic
1
1
1
0
1
0
Combin
ationalLogic
Combin
ationalLogic
PrimaryOutputs(PO)
PrimaryInputs(PI)
Scan
In
111100111
ScanEnable=1
ScanOut
Now,wearereadytoshiftoutthecapturedcombinationallogicresponses.However,whiledoingthat,wewillalsoshiftinthenexttestvector.
Thenexttestvectoris'111100111'.
NotethatwehavesetScanEnablesignalbackto1toenableshifting.
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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
Combin
ationalLogic
0
1
1
CombinationalLogic
0
0
11
0
1Combin
ationalLogic
Combin
ationalLogic
0111
PrimaryOutputs(PO)
PrimaryInputs(PI)
Scan
In
11110
ScanEnable=1
ScanOut
Hereisasnapshotoftheshiftoperation.Asyoucansee,wehaveshiftedout4bitsoftheprevioustestresponse,andatthesametimeshifted
in4bitsofthenewtestvectorinput.Thenewtestvectorbitsareshowninboldredinthefigureabove.
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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
Combin
ationalLogic
0
1
1
CombinationalLogic
1
1
11
0
0Combin
ationalLogic
Combin
ationalLogic
011000111
Primar
yOutputs(PO)
PrimaryInputs(PI)
ScanIn
ScanEnable=1
ScanOut
Atthispoint,wehavecompletelyscannedout(shiftedout)thetestresponsefortheprevioustestvector,andalsoscannedin(shiftedin)the
newtestvectorinput.
Theprocesscontinuesinthiswayuntilallthetestvectorsareapplied.
Note:Onpage5,Imentionedforce_PIandmeasure_PO.Actually,forindustrialcircuits,force_PIandmeasure_POisnotdone.Thisisbecauseprimaryinputsandoutputsareconnectedtoveryslowpads,andthesepadsarenottestedbystructuraltest.Youmayrealizethatinthiscase
the1stand4thcombinationalblockscannotbetested:1stblockcannotbetestedbecausewecannotapply inputsto it (force_PI).4thblock
cannotbe testedbecausewe cannot check itsoutput (measure_PO). This isusuallynot aproblembecause the circuits are surroundedby
wrapperscanflipflops.Thismeansthatthereisactuallynologicbeforethefirstlevelofscanflipflopsorafterthelastlevelofscanflipflops.
So,thecompleteDUTiscoveredbyscanflipflops.
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HowdoesScanWork? PreparedbyMahmutYilmaz
ScanChainOperationforDelayTestScanoperationfordelaytestisverysimilartostuckattest.Themaindifferenceisthatdelaytestneedstwoinputsinsteadofone.Thefirstinput
isalways
the
scanned
in
vector.
The
second
input
can
be
generated
in
two
different
ways.
Each
way
has
its
own
name:
(1)
Launch
on
Capture
(LOC)orbroadsidedelaytest,(2)Launchonshift(LOS)orskewedloaddelaytest.NowIwillshowhoweachofthesemethodsworks...
(1)Launch-on-Capture(Broadside)
DesignUnderTest(DUT)
Com
binationalLogic
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
CombinationalLogic
1
1
1
0
1
1
1
0
1
Com
binationalLogic
Com
binationalLogic
ScanEnable=0
Prim
aryOutputs(PO)
Prim
aryInputs(PI)
ScanOut
ScanIn
Thisisthesamefigurethatisshownonpage5.Assumethatalltheprocessuntilthispointisthesameasstuckattest.Youscannedinthetest
vector, forced thePIs,and theycreated someoutput responses forcombinationalblocks.This is step1.Youhavealreadyappliedyour first
vectorforthedelaytest.Guesswhatisthesecondvector?Thesecondvectorwilltheoutputresponsesofthecombinationalblocks.Eachblock
willgeneratethe2ndtestvectorforthenextstage.Sincethereisnostagebeforethe1stone,youneedapplyforce_PIonemoretime.
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HowdoesScanWork? PreparedbyMahmutYilmaz
Combin
ationalLogic
0
Primar
yInputs(PI)
ScanIn
Primar
yOutputs(PO)
1
1
1
0
1
1
0
1
0
0
0
1
0
0
11101101
0Combin
ationalLogic
CombinationalLogic
0
0
1 1
1
0
1
1
1
0
0
1
0
0
1
1
1
Combin
ationalLogic
DesignUnderTest(DUT)
ScanEnable=0
ScanOut
Ofcourse, inordertopushtheoutputresponsesofcombinationalblocks intoscanflipflops,weneedtotogglesystemclock.Oncewetoggle
thesystemclock(andapplythesecondPIforce),wewillgeneratethesecondtestvectorforthedelaytest,andeachcombinationalcircuitinput
willseean inputstate transition.The transitiononscan flipflopoutputs (whichare inputs to thenext stagecombinationalblock)willbeas
follows(startingfromtheclosesttoscaninflop): 100101110 >010010111
Thesecondinputvectorwillgenerateoutputresponsesjustlikethefirstone.And,youneedtocapturetheseresponsesjustlikewedidbefore,
by toggling the systemclock.However,now there isadifference:Youhave to toggle thesystemclockat the realoperating frequency:This
meansthattheperiodbetweenthefirstclocktoggleandsecondclocktoggleshouldbeequaltofunctionalclockperiod.Inthisway,youwill
capturethedelaytestresponsesatthefunctionalfrequency.
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HowdoesScanWork? PreparedbyMahmutYilmaz
HereisatimingdiagramoftheLOCprocess(source:MentorGraphicsScanandATPGProcessGuide,August2006):
Asyoucanseeabove,weshiftthetestvectorusingaslowclockfrequency.Then,wesetscanenableto0anddisablescanmode.Inthenext
step,we toggle the clock first time to launch a transition in combinational blocks.After that,we toggle the clock again (at the functional
frequency)tocapturethefinalresponsesofthecombinationalblocks.Thelaunch&captureeventshappenatfunctionalfrequency.Finally,we
shiftedoutthecapturedresponsesusingtheslowclockfrequency.
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HowdoesScanWork? PreparedbyMahmutYilmaz
(2)Launch-on-Shift(Skewed-Load)
Design
Under
Test
(DUT)
Combinatio
nalLogic
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
CombinationalLogic
1
0
1
1
1
1
1
1
0Combinatio
nalLogic
Combinatio
nalLogic
ScanEnable=1
PrimaryOutputs(PO)
PrimaryInputs(PI)
Scan
Out
ScanIn
Thisisthesamefigurethatisshownonpage5and10.So,westartasusual:Assumethatalltheprocessuntilthispointisthesameasstuckat
test.Youscannedinthetestvector,forcedthePIs,andtheycreatedsomeoutputresponsesforcombinationalblocks.ForLOS,wedon'tcare
abouttheseinitialoutputresponses.Thisisstep1.Youhavealreadyappliedyourfirstvectorforthedelaytest.Sincethereisnostagebefore
the1st
one,
you
need
apply
force_PI
one
more
time.
Note
that
Scan
Enable
signal
is
still
at
active
value
1.
This
is
because
we
have
not
yet
done
withshifting.Weneedtoshiftonemoretimetocreatethesecondtestvectorforthedelaytest.
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HowdoesScanWork? PreparedbyMahmutYilmaz
Combination
alLogic
PrimaryOut
puts(PO)
PrimaryInpu
ts(PI)
ScanIn
ScanEnable=1
DesignUnder
Test
(DUT)
Combination
alLogic
Combination
alLogic
Combinatio
nalLogic
0
0
1
1
0
1
1
1
0
0
1
0
0
0
1
0
0
11101101
0
1
0
0
1
0
1
1
1
0
ScanOut
Notethatasmentionedinthepreviouspage,thefirstvectorofthedelaytestis(startingfromtheclosesttoscaninflop): 100101110
Thesecondtestvectorisgeneratedbyshiftingonemoretime,andinsertingonemorebitfromScanIn,2ndvectoris: 010010101
Justafteryoushiftthelastbit(andlaunchedatransitionbyapplyingthesecondvector),youhavetoforceScanEnableto0,andalsotogglethe
systemclockatthefunctionalfrequency.Thelasttoggleofthesystemclockwillcapturethedelaytestresponses.Finally,youwillscanoutthe
responsesasusual.
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HowdoesScanWork? PreparedbyMahmutYilmaz
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YoucanseethatweneedtohaveaveryfastScanEnablesignalinordertouseLOS.ScanEnableshouldbeabletoswitchfrom1to0withina
very
short
time.
This
is
usually
a
difficult
process
because
Scan
Enable
is
not
designed
to
operate
at
high
frequencies.
Due
to
this
reason,
many
industrialdesignsuseLOCinsteadofLOS.(TherearesomedesignsthatuseLOS.ThereareworkaroundstofastScanEnablesignalrequirement,
butIwillnotgointodetailsfornow.)
Asyoucanseeabove,weshiftthetestvectorusingaslowclockfrequencyuntilthelastbit.ThelastshiftedbitcreatestheLaunchevent.Then,
beforewe toggle thesystemclock tocapture responses,wesetscanenable to0anddisablescanmode.Thishas tohappenvery fastsince
Launch & Capture event happen at high frequency. In the next step, we toggle the clock again to capture the final responses of the
combinationalblocks.Finally,weshiftedoutthecapturedresponsesusingtheslowclockfrequency.
HereisatimingdiagramoftheLOSprocess(source:MentorGraphicsScanandATPGProcessGuide,August2006):