Download - Half Adder
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Utkarsh Mishra/ 101125/ A5 Page 1
Experiment-1
AIM: Design,synthesis and stimulate the half adder circuit using Xilinx Software.
1. Data flow modelling
2. Structural flow modelling
3. Behavioral modelling
4. Mixed modelling
Software used: Xilinx 5.2i.
Activity-1: Write VHDL code using Data Flow Modeling
RTL Schematic
Simulation Result:
Synthesis Result:
Number of Slices: 1 out of 192
Delay: 8.234ns
Device Family: Spatan2
Activity 2: Write VHDL code using Behavioral Modeling.
RTL Schematic:
Simulation Result:
![Page 2: Half Adder](https://reader036.vdocuments.mx/reader036/viewer/2022081803/545a71dcb1af9f39378b5cdc/html5/thumbnails/2.jpg)
Utkarsh Mishra/ 101125/ A5 Page 2
Synthesis Result:
Number of Slices: 1 out of 192 0%
Delay: 8.234ns
Device Family: Spatan2
Activity 3: Write VHDL code using Structural Modeling .
RTL Schematic
Simulation Result:
Synthesis Result:
Number of Slices: 1 out
of 192 0%
Delay: 8.234ns
Device Family: Spatan2
![Page 3: Half Adder](https://reader036.vdocuments.mx/reader036/viewer/2022081803/545a71dcb1af9f39378b5cdc/html5/thumbnails/3.jpg)
Utkarsh Mishra/ 101125/ A5 Page 3
Activity 4: Write VHDL code using Mixed Modeling
RTL Schematic:
Simulation Result:
Synthesis Result:
Number of Slices: 1 out of 192 0%
Delay: 8.234ns
Device Family: Spatan2
Conclusion:
Simulation result waveform are shown.
All the modelling is having equal number of slices i.e. 1 out of 192.
All the modelling is having equal amount of Delay i.e. 8.234ns.