Download - GLAST LAT Project December 6, 2002

GLAST LAT Project December 6, 2002

Tracker, WBS 4.1.4 1

GLAST Large Area Telescope:GLAST Large Area Telescope:

Tracker SubsystemWBS 4.1.4

Tracker ASICs

Robert JohnsonSanta Cruz Institute for Particle PhysicsUniversity of California at Santa CruzTracker Subsystem Manager

[email protected]

GammaGamma--ray Large ray Large Area Space Area Space TelescopeTelescope



OutlineOutline

• Introduction/Summary• System overview• Requirements• GTFE designs• GTFE performance and issues• GTRC design• GTRC test results and issues• Test plan



SummarySummary

• Tracker ASIC tests indicate that the design meets our requirements and goals if a few corrections are made in the production run:– Bipass one cell in the GTFE-G to improve yield. The change has been

verified by FIB.– Fix logic errors in the GTRC3 related to TOT and parity reporting.– Improve timing margin by changing the GTRC clock edge for receiving

GTFE data (or raise DVDD, or lower frequency).• To hold the LAT schedule, the ASIC production must go out now (critical

path leading to the Tracker qualification unit).• To guarantee that we do not come up empty handed 4 months from now,

when the ASICs are needed, we must have a backup plan consisting of submission of existing, unmodified designs. In the worst case this means– No reliable TOT information (not a science requirement).– Incomplete reporting of possible bit errors.– Higher power (by about 30W).– Possible calibration complications due to GTFE-F2 comparator behavior.



Tracker Readout Block DiagramTracker Readout Block DiagramFailsafe/redundancy scheme:• Serial, LVDS readout and control lines.• Two readout and control paths for every 64-channel front-end chip.• Any single chip can fail without preventing the readout of any other.• Either of the two communications cables can fail without affecting the other.

24 64-channel amplifier-discriminator chips for each detector layer

2 readoutcontroller chipsfor each layer

Con

trol

sig

nal f

low C

ontrol signal flow

Data flow to FPGAon DAQ TEM board.

Data flow to FPGAon DAQ TEM board.

Control signal flow

Data flow

Nine detector layers are read out on each side of each tower.

GTRC

GTFEGTFE

GTRC

GTRC

GTRC

GTRC

GTRC

9-998509A22

• Trigger output = OR of all channels in a layer.

• Upon trigger (6-fold coincidence) data are latched into a 4-event-deep buffer in each front-end chip.

• Read command moves data into 1 of 2 GTRC buffers.

• Token moves data from GTRCs to TEM.



TMCM (Readout Module)TMCM (Readout Module)• 8-layer polyimide PWB• Top edge thickened and machined to a 0.64

mm radius• 1-layer flex circuit (“pitch adapter”)

bonded over the radius• 24 64-channel GTFE chips• 2 GTRC chips• 2 nano connectors• SMT parts• Steel mounting screws + transfer adhesive

Readout IC

Machined corner radius with flex circuit bonded around the curve

TMCM, attached by screws

Detector

Tray Structure

Bias circuit

High-thermal conductivity transfer adhesive

Readout IC



Detector

Tray Structure

Bias circuit




Detector

Tray Structure

Bias circuit


24.58mm 18.0mm

359.0mm

Grounding Screws3 Total

Mounting Screws, 1 of 8

Connector, 1 of 2

GTFE, 1 of 24GTRC, 1 of 2



TKR Electronics RequirementsTKR Electronics Requirements

• Details of the requirements are in– LAT-SS-17 Performance requirements– LAT-SS-134 Mechanical & Thermal requirements– LAT-SS-152 Electronics requirements

• The major challenges are– Low power: <168 W of conditioned power

• Less than 0.29 W per TMCM or 190 µW/channel– Low noise occupancy: (noise trigger rate <500 Hz)

• The trigger requires occupancy less than 5/100,000 ch/trigger• Readout and onboard processing requires <1/10,000

ch/trigger– Compact packaging: bring signals around the tray corner– Manufacturing and QC: 884,736 channels in outer space– Reliability: design, testing, redundancy



Some Detailed RequirementsSome Detailed Requirements

• Internal charge injection for calibration and test, with a DAC to control the pulse height and a mask to select any set of channels.

• Threshold uniformity: <15 mV rms across 64 channels.• Threshold control per GTFE chip by an internal DAC.• Readout speed & dead time: less than 10% at 10 kHz cosmic rate.• TOT: measure up to 4 MIPs.• Non-destructive readback of configuration registers.• 2-bit word sent with the trigger and returned by the GTFE chip,

to ensure that events are never mixed up unknowingly.• Layer-OR jitter <±250 ns for a charge deposit > 0.5 MIP.• Reliability:

– Redundant readout paths.– Redundant power paths.– Protection against power shorts.

• Radiation hardness; 4 kRad TID; >37 MeV/mg/cm2 SEL thresh.• Passive cooling; temperature monitoring.



Tracker Electronics DocumentsTracker Electronics Documents

Tracker Tower Electrical Test PlanLAT-TD-191

Test Plan for the Tracker ElectronicsLAT-TD-153

Tracker Front-end Readout ASIC Prototype Test PlanLAT-TD-246

Test Plan for the Tracker Preproduction ASICsLAT-TD-881

Polyswitch Resettable Fuse SpecificationLAT-SS-1116

Tracker Grounding and Shielding PlanLAT-TD-173

Flex Cable Procurement, QA, and Qual RequirementsLAT-PS-1132

Tracker Flex Cable SpecificationLAT-SS-175

Tracker Multi-Chip Module SpecificationLAT-SS-171

Tracker Readout Controller ASIC SpecificationLAT-SS-170

Tracker Front-end Readout ASIC SpecificationLAT-SS-169

Tracker Readout Electronics Conceptual DesignLAT-SS-168

Tracker Electrical Interface SpecificationLAT-SS-176

Tracker Subsystem Level-IV Electronics SpecificationLAT-SS-152



Tracker Electronics DocumentsTracker Electronics Documents

Tracker Electronics Parts ListLAT-TD-179

Trigger Noise Rate Measurements on a Tracker LadderLAT-TD-1060

Self shielding of the TKR and ASIC TID RequirementsLAT-TD-1165

LAT Tracker ASICsLAT-TD-386

TOT Requirements for the Tracker ElectronicsLAT-TD-244

Tracker Reliability AnalysisLAT-TD-178

Test results on the Tracker ASIC prototypesLAT-TD-1090

First Calibration Scan Results on a Tracker LadderLAT-TD-1023

Test Results for the GTFE64d PrototypeLAT-TD-545

Single-Channel Noise Occupancy in the BTEMLAT-TD-364

Single-Event Effects Tests of the Tracker Readout ASICLAT-TD-333

Tracker Electronics Radiation Test Plan at LNLLAT-TD-1059

Tracker Multi-Chip Module Test PlanLAT-TD-249

Tracker Readout Controller ASIC Wafer Test ProcedureLAT-TD-248

Tracker Front-end Readout ASIC Wafer Test ProcedureLAT-TD-247



F.E. Readout Chip (GTFE)F.E. Readout Chip (GTFE)• Schematics-based design, using standard cells for logic.• Manual layout of the analog channel, I/O cells, memory, global routing.• Automated place-and-route of the logic blocks.• Two versions under test:

• F2 (AC coupling from shaper to comparator)• G (DC coupling from shaper to comparator)

64 amplifier-discriminator channels.

4-deep event memory (addressed by TEM)Custom layout 2 custom DACs

Trigger and Data mask registersStandard-cell auto route

Control logic, command decodersStandard-cell auto route

Cap

Calibration mask and capacitors

I/O pads and protection structures



GTFE Block DiagramGTFE Block Diagram

S

OUTA

B

64

64

64

641

2DC

Q

DC

Q

LEFT/RIGHT

DEAFMODE

DATA OUT

64

67 X 4

EVENT BUFFER

2

2

W_ADDR

R_ADDR

WRITE STROBEL1T

READ CMD

WRITECONTROL

READCONTROL

LOAD

DATAFROMPREVIOUSGTFE

DATA READ SHIFT REGISTER

DATA MASK & READOUT REGISTER

TRIGGER MASK & READOUT REGISTER

DISCRIMINATORS

SHAPERS

PREAMPLIFIERS

CALIBRATE STROBE

LEFT COMMANDDECODER

RIGHT COMMANDDECODER

CMDL

CLKL

CMDR

CLKR

RESET

7 7

DAC REGISTER

CALIBDAC

THRESHDAC

64 ANALOG INPUTS

S

CTRLREG

FAST-OR

MODEREG

SEL ADDRESSED

(TRI STATE)

LEFT COMMAND SELECT

DATA HIT

DATA HIT

LOAD/READ TRIGGER MASK

LOAD/READ CALIBRATE MASKLOAD/READ MODE REGISTERLOAD/READ DAC REGISTERCALIBRATE STROBE

MUX

641TRIGGER FROM PREVIOUS GTFE

FROM SILICON STRIPS

CALIB. MASK & READOUT REGISTER

EVENT_TRIG

EVENT_DATAEVENT_OR

• 64 amplifier-discriminator channels

• 7-bit threshold DAC• Calibration mask register• 7-bit calibration DAC• Trigger mask register and trigger

layer-OR• Data mask register• 4-deep event buffer• Pair of redundant command

decoders• Pair of redundant trigger

receivers• Leftward readout register• Rightward readout register• LVDS I/O cells



F2 Version ShaperF2 Version Shaper

1 per 64 channels

No source-follower stage



GG--Version ShaperVersion Shaper

1 per 64 channels



Readout Controller Chip (GTRC3)Readout Controller Chip (GTRC3)

I/O I/O

CMDDECODER

CONTROLREGISTER

REGISTERREADBACKCONTROL

GTFEREADOUTCONTROL

EVENTMEMORY

0

EVENTREADOUTCONTROL

TRIGGER

FASTOR

I/O

I/O

TOT

NSDATA_IN

NTOKEN_OUT

NSDATA

TOKEN

NRESET

CLK

NSCMD

NTACK

NTREQ TREQ_IN

RD_IN

TACKB

SCMDOUT

CLKB

RESETB

CTRLREG

EVENTMEMORY

1

• All digital• Tanner standard-cells, except for

• LVDS I/O cells.• SEU hardened configuration

register.• RAM (64 hits, 2 buffers)

• Design in VHDL; synthesis, auto place and route.



Tracker ASIC Test ProgramTracker ASIC Test Program

• G. Haller’s Electronics & DAQ group (D. Nelson, M. Huffer, C. Brune, J. Olsen, et al.): system testing with the official TEM-based EGSE; GTRC test and debug.

• UCSC group (R. Johnson, M. Sugizaki, Z. Wang, N. Spencer, M. Wilder, M. Ziegler, et al.): wafer probing; analog performance; GTFE debugging, MCM testing and MCM production test system.

• Pisa group (L. Latronico, L. Baldini, G. Spandre, J. Cohen-Tanugi, et al.): tray and tower-level testing.

• Padova group (R. Rando, et al.): radiation testing.• Relevant test plans for today’s results:

– LAT-TD-153, Tracker electronics test plan– LAT-TD-881, test plan for the preproduction ASICs– LAT-TD-246, GTFE prototype test plan– LAT-TD-247, GTFE wafer test procedure– LAT-TD-248, GTRC wafer test procedure– LAT-TD-249, MCM test plan– LAT-TD-1059, radiation test plan



GTFE Wafer TestingGTFE Wafer Testing

• 17 wafers with 45 chips of each type were probed.• A complete set of test vectors was executed, and threshold scans were

made.• All digital functionality was checked, except for I/O on the chip-to-chip

connections (due to problems with the probe card).• The yield was excellent, except for about 15% of the G chips that have a

threshold instability (more on this later).

GTFE Version-F2 GTFE Version-G

Yield for digital tests 201 through 207.

95.5% 94.5%

Yield including threshold scan test.

94.8% 79.8%



Threshold Scans (Ladder + miniThreshold Scans (Ladder + mini--MCM)MCM)

10 20 30 40 50Threshold (DAC Counts)

0

20

40

60

80

100

Effi

cien

cy Channel C241

Mean = 40.17 Sigma = 5.78

10 20 30 40 50Threshold (DAC Counts)

0

20

40

60

80

100

Effi

cien

cyChannel C286

Mean = 33.16 Sigma = 6.82

G chip channel

F2 chip channel



Threshold ScansThreshold Scans

• 3 full-length ladders with mini-MCMs have been tested:– Hold the charge injection constant and scan the threshold– Hold the threshold constant and scan the charge injection

0 40 80 120Gain (mV/fC)

0

500

1000

1500

2000

EN

C (e

lect

rons

)

G Version; each chipF2 Version; each chip

Ladders 10 and 11 Threshold Scan Averages

This is for about 1.6 fC charge injection. The gain is nonlinear.



Threshold ScansThreshold Scans

17114546.9%103.364G5

18914498.1%93.364G4

14913677.2%106.964G3

31222207.6%66.859F22

22721596.6%68.760F21

15621025.5%90.162F2011

110V

28920116.4%88.361F25

20120088.2%93.062F24

10312673.9%123.461G3

14514245.6%114.763G2

12013615.0%126.464G1

25016576.8%94.363G010

80V

Std Dev

ENC (elec)

Std Dev

Gain (mV/fC)

# ChTypeChipLDRThe charge injected was about 1.6 fC.



ChargeCharge--Injection Scan (THR=22)Injection Scan (THR=22)

9615304.4%96.51.1064G5

14815787.2%88.51.2064G4

9914365.6%97.01.1064G3

27819626.8%65.11.6364F22

10720485.8%67.31.5764F21

13221195.9%83.61.2764F20

Std DevENC (elec)

Std DevGain (mV/fC)

Q (fC)

# ChTypeChip



Problem with Last 2 Channels of F2Problem with Last 2 Channels of F2

0 10 20 30 40 50 60Threshold DAC Setting

0

20

40

60

80

100

Effi

cien

cy

C318C319C382C383C446C447

Channels 62 & 63 on 3 F2 ChipsHypothesis: feedback from comparator to shaper via a test pad that exists only on each of these two channels. (Double-pulses are seen on an oscilloscope.)



0 10 20 30 40 50 60

Threshold DAC Setting

0

20

40

60

80

100

Hit

Effi

cien

cy

G Chip, with 32 Channels Pulsed Simultaneously


0

20

40

60

80

100

Effi

cien

cy

G Chip, 8 Channels Pulsed Simultaneously

Simultaneous Multiple ChannelsSimultaneous Multiple Channels

No load on the amplifier inputs.



F2 VersionF2 Version

10 20 30 40 50 60Threshold DAC Setting

F2 Chip, 8 Channels Pulsed Simultaneously


0

20

40

60

80

100

Effi

cien

cy

F2 Chip, With 32 channels Pulsed Simultaneously

No load on the amplifier inputs.

Note: the noise measurements presented above were made by simultaneously pulsing 8 channels per chip.



GG--Version Unstable ChipsVersion Unstable Chips

• About 15% of the G-version chips show oscillations on the Layer-OR output with the threshold set to >5 DAC counts (about 0.24 fC), with some still oscillating at threshold >30 DAC counts.

• The problem was isolated to the “threshold conditioner” cell. Good chips could be made bad and vice-versa by adjusting the bias of the output driver of this cell (using a probe on internal test pads).

• 8 of the worst oscillating chips were modified by FIB to bipass this cell, and they all behaved normally afterwards on mini-MCMs. So far one was connected to a ladder and had excellent noise scans. (One more FIB chip was damaged and is completely dead.)

• Spice simulations show that the impedance of the threshold bus is greatly reduced and the amount of “kick-back” from the comparator is reduced by more than 10 when this cell is removed.

• 24 “good” chips were selected by the wafer-probing data and tested on a full-size MCM. All behaved well on the MCM, including over the temperature range –30C to +50C.



GG--Version ShaperVersion Shaper

1 per 64 channels



GG--Version FIB EditVersion FIB Edit



Trigger RatesTrigger Rates

0 1 2 3Threshold/Gain (fC)

100

101

102

103

104

105

106

Rat

e (H

z)

G0G1G2F3F21F22

Trigger Rate per Chip (64 Channels)

1.3 fC=1/4 MIP

All 64 channels in just one chip were enabled, and the Layer-OR rate was measured by a frequency counter for each threshold setting. For ladder 0:

Long TOT pulses; look like cosmic rays



Noise OccupancyNoise Occupancy

0 100 200 300Channel Number

0

2

4

6

Noi

se H

its

Ladder 0, 80V bias, 1.3 fC threshold, 1.5 million triggers.

Measured on 2 ladders so far. About 10−6 per trigger.

G F2



Effect of Readout on NoiseEffect of Readout on Noise

• Ladder 11, biased at 110V.• Set thresholds at 1.3 fC (using gains measured in the calibration

charge-injection scan).• Load a hit pattern into the GTFE memory by charge injection (every

8th channel hit; other patterns will be investigated). • Monitor the Layer-OR with all 384 channels enabled.• Execute a test vector involving a complete readout sequence, and

count how many pulses appear on the Layer-OR during execution of the vector. Repeat 1000 times.

• Execute a test vector involving only a clock (no commands) and count the Layer-OR pulses. Repeat 1000 times.

• Layer-OR rate with clock only (no readout): 448 Hz.• Layer-OR rate with readout: 440 Hz.

No effect.



GTFE TimeGTFE Time--OverOver--ThresholdThreshold

0 10 20 30 40Injected Charge (fC)

0

20

40

60

TOT

(mic

rose

cond

s)Time Over Threshold, GTFE-G

External InjectionInternal, Low RangeInternal, High RangeSpice Simulation

Evidence of some problem with our DAC calibration measurements.

Timing out the counter at 50 µs gives a range of about 5.2 MIPs.

Measure the Layer-OR width with internal (both ranges) and external charge injection into a single channel.



GTFE TimeGTFE Time--OverOver--ThresholdThreshold

100 101 102 1032 3 4 5 6 7 2 3 4 5 6 7 2 3 4 5 6 7 2 3 4 5 6 7

Injected Charge (fC)

0

50

100

150

TOT

(mic

rose

cond

s)

Time Over Threshold, GTFE-G

External InjectionInternal, Low RangeInternal, High RangeSpice Simulation

The TOT saturates at about 150 µs when the preamp saturates.

VDD=2.5 V



Example Shaper WaveformsExample Shaper Waveforms

0 5 10 15 20t (microseconds)

-100

0

100

200

300

V (m

V)

Cal DAC=8Cal DAC=26Spice, 14 mVSpice, 42 mV

GTFE64G FIB, Channel 2



Example Shaper WaveformsExample Shaper Waveforms

0.0 2.5 5.0 7.5 10.0 12.5time (microseconds)

0

50

100

150

V (m

V)

F2 Chip Shaper Output; No Input Load

Comparator transition

CAL-DAC=30CAL-DAC=20



MCM Power MeasurementMCM Power Measurement

134.3 mW

134.3 mW

DVDD 2.5 V

address 5

138.5 mW28.0 mW77.4 mW20 MHz, F2

138.5 mW39.3 mW77.4 mW20 MHz, G

82.8 mW39.3 mW77.4 mWNo Clock, G

DVDD2.5 V

address 0

AVDDB2.5 V

AVDDA1.5 V

168 W

10.5 W

Allocation

139

8.66

0.244

0.240

F2 (W)

14516 Towers

9.05Tower

0.255MCM Address = 0

0.251MCM Address > 0

G (W)



DAC CalibrationDAC Calibration

0 10 20 30 40 50 60DAC Setting

0.0

0.1

0.2

0.3

Vol

tage

Threshold DAC at VDD=2.5V

Intercept=7.37 mV

Slope=4.94 mV


0.0

0.2

0.4

0.6

Vth

-Vre

f (V

)

High RangeFit

Intercept: 9.53 mVSlope: 10.1 mV

Threshold DAC Calibration at VDD=2.5

0 20 40 60DAC_Value Lo Range

0

20

40

60

80

DA

C O

utpu

t (m

V)

2.0147 + 1.4340*x

0 10 20 30 40 50

DAC Value, High Range

0

100

200

300

400

500

600

DA

C O

utpu

t (m

V)

14.3137 + 11.4024*x

CAL-DAC

THR-DAC



DAC CalibrationDAC Calibration

12.9 mV/cnt10.1 mV/cnt12.9 mV9.53 mVThreshold High

4.5 mV/cnt4.94 mV/cnt4.5 mV7.37 mVThreshold Low

14.6 mV/cnt11.4 mV/cnt15.0 mV14.3 mVCal High

1.53 mV/cnt1.43 mV/cnt1.57 mV2.01 mVCal Low

Slope Predicted

Slope Measured

Intercept Predicted

Intercept Measured

Range

• Except for current-mirror errors, the intercept should be equal to the slope.

• Deviation from this expectation as well as the Spice prediction casts some uncertainty on the measurements.



GTRC & MCM TestingGTRC & MCM Testing

• The GTRC3 chip has been found to have these logic bugs:a) The TOT measurement is not buffered properly and will not stay

aligned with the hit data at high rates.b) The parity is not calculated correctly for data read out from the

right hand side.c) Parity errors in the commanding are not reported properly.

• These bugs have been understood and fixed in the VHDL.• Bugs (a) and (b) were quickly found and fixed in the GTRC5

submission, due to be received in a few days.• All bug fixes and the following modifications are being prepared for

the GTRC6 submission:– Latch data from the GTFEs on the falling clock edge, to improve

the timing margin.– Remove the data field from data-less commands.

• The revised VHDL is under test in an FPGA version of the GTRC, working on boards with actual GTFE chips.



Timing/Voltage MarginsTiming/Voltage Margins

OKOK252.9

NGNG30

NGOK25

OKOK20

2.8

NGNG25

NGNG23

NGOK22

OKOK20

2.6

NGNG20

OKOK102.5

GTFE CtrlReg

GTFE DataClock (MHz)DVDD (V)

Measured on a full-scale MCM (24 GTFE chips), but with the clock/cmd bus termination resistors still at the wrong end.



GTFE Register ReadbackGTFE Register Readback

The GTFE internal delays are double the Spice prediction until all extracted trace parasitics are included. Then we get good agreement. The overall delay could be reduced by increasing the size of several drivers and/or by realigning the data with the clock immediately before the GTFE output driver.

~10Delay in charging up the MCM bus and receiving the bit into the GTRC

10Delay in getting the signal to the GTFE output pad

6Delay in establishing the DAC output onto the long internal GTFE trace.

10Delay of GTFE internal control logic in getting the clock to the read register.

4Receiving the clock into the GTFEGTFE internal; measured on test pads.

2.5 V

~10Driving the MCM clock bus from the GTRC

Delay (ns)Components of the Round-trip Delay

Total is nearly 50 ns!



Reading GTFE Data into GTRCReading GTFE Data into GTRC

• The GTFE delays by about ½ clock cycle, as shown above.• Delays sending the clock out of the GTRC and receiving the

differential data into the GTRC account for most of another ½ cycle, leaving little margin at 2.5V.

DVDD=2.5 V

MCM Clock

GTFE Data Out



Solutions to the Timing ProblemSolutions to the Timing ProblemSelect one of the choices below:

1. Increase the operating voltage to 2.9 V for AVDDB and DVDD.• MCM power increases by ~52 mW. LAT power increases by about

30W, putting the Tracker 7W over allocation.

2. Lower the system clock to 18 MHz.3. Lower the Tracker clock to 10 MHz, keeping the system at 20 MHz.4. Latch the data into the GTRC on the falling clock edge.

• Depends on the fact that the delays now put the data edge very close to the GTRC clock rising edge.

• We would be in trouble if the delays changed in the next run to much shorter values. Unlikely, but we put in a programming wire-bond pad to revert to the clock rising edge (GTRC6).

• If the system is run on a slow clock, then the data get latched a clock cycle early. GTRC has to be reprogrammed to adjust.

• There will probably be a small frequency range <<20 MHz where the system cannot be adjusted to read properly both registers and data without programming the GTRC in between.



Misc. Other TestsMisc. Other Tests

• GTRC LVDS levels (address=0 and address≠0).• Detailed measurements on GTFE I/O cells (LAT-TD-545).• Radiation testing at LNL (Italy) on a mini-MCM.

– Only the GTRC was tested so far.– 5 ions from Si to Au.– TID of 30 kRad. GTRC still operated at 20 MHz.– No latch-up, even at LET=82 MeV/mg/cm2.– SEU rate in the configuration register was consistent with the

earlier test chip (LAT-TD-333).



Electronics Test PlanningElectronics Test Planning

• Before GTRC submission:– Complete check-out of the GTRC6 VHDL on the 3 test boards,

each with 2 GTRC-FPGAs and 2 GTFEs.• ASAP:

– Complete and test the FPGA test board with 24 GTFEs.– Tests with high-rate readout and random trigger:

• High-rate test of a ladder/mini-MCM using a beta source.• Self trigger at high rate on noise in one or a few channels, both

on a mini-MCM and the FPGA board.– Connect the mini-MCM loaded with FIB G chips to a ladder and

test.• EM MCM production at Teledyne: starting next week test boards

coming off of their production line (LAT-TD-249).



Electronics Test PlanningElectronics Test Planning

• 6 EM MCMs to be delivered to the electronics group for their own tests.

• 2 EM MCMs for environmental testing at UCSC and SLAC.• 8 MCMs on functional engineering-model trays.

– One tray for environmental testing in Italy.– Four trays (6 MCMs) for mini-tower testing at SLAC.

• First cosmic-ray tests since the BTEM tower.• Develop and execute tower-level test code (LAT-TD-191).

• Production wafer testing:– Redo and improve the GTFE probe card and test system.– Redo and test on existing wafer the GTRC probe card.– M. Ziegler working with D. Marsh to bring the UCSC wafer-

probing area into compliance (contamination control, etc.).– Work in progress to incorporate this into the database.



ConclusionConclusion

Tracker ASIC Fabrication Proposal• Details still need to be agreed upon following and depending upon

the conclusion of this review.• Front-end ASIC

– Submit the GTFE-G2 (G version with “threshold conditioner” removed). The layout is verified and ready.

– Backup with the GTFE-F2 (no changes). Begin a study of the operational implications of its performance, to be prepared.

• Readout Controller ASIC– Submit the GTRC6, after completion of verification in the FPGAs.– Backup with the GTRC3 (no changes) and the GTRC5. No cost

impact of this. We will have the GTRC5 prototype very soon to test.

– Study further implications of having to use the GTRC3.

Download - GLAST LAT Project December 6, 2002

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