Download - Fujitsu ARM Cortex Design Support
Fujitsu ARM CortexDesign Support
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Fujitsu Semiconductor Europe
FactsheetFujitsu ARM Cortex DesignSupport
FASP Support (Fujitsu ARM® based SoCPrototyping Kit)� FASP is a reference design concept ofARM based SoC
� All Fujitsu IPs are integrated into areference design
� FASP consists of a reference design (RTL),simulation environment, example program(boot code), synthesis environment, netlist, verification environment (FV script andexample STA scripts)
� FASP enables the customer to shorten thedesign TAT and verification TAT
� FASP will support the following ARM cores:- CortexTM-M3- Cortex-A9- Cortex-R4F- Cortex-A5 (planned)- Cortex-A15 (planned)
ARMONDE-A9 (ARM Evaluation Chip)This ARM evaluation chip is targeted to develophigh performance ARM based SoCs andcontains therefore the Cortex-A9, Cortex-R4and Cortex-M3 cores. In the future, the EV chipwill have implemented Fujitsu advanced IPslike PCIgen2, SATAgen2, USB3.0, etc.This EV chip enables designers to develop IPdrivers and OS. Also, the TAT for SoCprototyping will be much shorter.An Evaluation Board will also be provided withthe ARMONDE-A9. This board is available withan LCD monitor (touch panel) and FPGA foruser logic extension. The following deliverablesare available with the board:� FPGA reference design� Software (OS: Linux, ITRON or Android)� Drivers for IPs� ARMONDE-A9 Block Diagram� IPs used on ARMONDE-A9 (see table on P2)
Cortex-A9 Block diagram
Cortex-A9Core Bock
Debug APB
FPU/NEON PTMI/F
GenericInterrupt Controland Distribution
Cortex-A9 CPU
I-Cache D-Cache
FPU/NEON PTMI/F
Cortex-A9 CPU
I-Cache D-Cache
FPU/NEON PTMI/F
Cortex-A9 CPU
I-Cache D-Cache
FPU/NEON PTMI/F
Cortex-A9 CPU
I-Cache D-Cache
PTM PTM PTM PTM
CTM
CTI
ROM Table
APB_MUX
APB_SYNC
APB_DEC
Timers/Watchdog
Snoop Control Unit(SCU)
AcceleratorCoherence Port
(ACP)
Bus Interface Unit
PL310
Debug APB
ATB ATB ATB ATB
ACP
CrossTrigger
InterruptSignals
64-bit AXI Interface Optional 64-bit AXI Interface
ARMONDE-A9 Block diagram
USB2.0Host/Func
I2S TPIF SPI/I2C/MCC
DMAC
ARMONDE-A9
Controller Block AP Block
DDRC BlockHSIO Block
GPUBlock
ARM IP
ADK/Primecell
FSL IP
3rd IP
UDL Extention
PCIe RC/EPGen2-4Lane
PCIe RC/EPGen2-4Lane SATA Gen2 Host USB3.0 Func
Cortex-R4F250MHz
Cortex-M3125MHz
Cortex-A9 2MP500MHz
BP137
L2CC (PL310)
DMACACP
64-bit
64-bit
DAPAHB-AP
APB
DAPSystem APBAPB
APB
NIC-301 AXI 300MHz 64-bit
NIC-301 AXI 300M/64-bit
NIC-301 AXI 300MHz 64-bit
AHB BusMatrix 75MHz
BP137BP137BP137
VIC
TIMER/WDT
AHB BusMatrixAHB BusMatrixAHB BusMatrix
H2PBB H2PBBSRAM64k x 2
IPCU
H2PBB H2PBB CCPB
MEMC
SFI
TIMERWDT
DMACSDRAMC
Reg.
MRBC, CRG11,EXIU, GPIO, UART
BB
BB
BB
LCDIF x 2 2DGPU 3DGPU
Mul
ti-po
rtM
EMC
SRAM
SRAM
DMAC
GMAC
NoE
GMAC
NoE
H2XBB
GMAC
SDIO
RELCSRAMFLASH
DDR3600
Operating frequency (except as otherwise stated) AXI= 64-bit/300MHz, AHB= 32-bit/150MHz, APB= 32-bit/75MHz
64-bit
64-bit
32-bit
SRAM16k
SRAM16k
DMAC
32-bit
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Factsheet Fujitsu ARM Cortex Design Support
FSEU-A52-28SEPT11
[email protected]://emea.fujitsu.com/asic
All company and product trade marks and registered trademarks used throughout this literature are acknowledged asthe property of their respective owners.
IPs on ARMONDE-A9
Category IP Name Descriptions
Processor Cortex-A9 MPcore Dual-core, 500MHz, L1 cache I/D=32KB/32KB, L2 cache = 512KB, ACP-DMACortex-R4F 250MHz, L1 cache =16KB/16KB, TCM_A=64KB, TCM_B0=32KB, TCM_B1=32KBCortex-M3 125MHzGPU OpenGL ES1.1/OpenGL ES2.0/OpenVG1.1, LCD Controller (2-ch)
Interface Macro PCIe PCI Express Gen2, Root/Endpoint, 4-lanes (2-ch/SoC IF + FPGA extension)SATA Serial ATA Host Gen2USB3.0 USB3.0 FunctionUSB2.0 HDC USB2.0 Host/Function DMACGMAC Ethernet MAC 1000/100base, 802.3az (LPI), GMII, IEEE1588SDIO UHS-1(eMMC)UART UART (2-ch)I2C I2C (1-ch)I2S I2S (1-ch) + DMACSSP (PL022) Compatible with Motorola SPI, TI SSI and National Semiconductor MicrowireNoE 2ch IPSec Network Off-load Engine with GMAC4MT (700Mbps half duplex IPSEC)TPIF Touch Panel Interface (Multi-touch detection)
Memory I/F SDRAMC DDR2/3-600MHz 32-bitMEMCS Flash/SRAM ControllerSPI Quad Serial Flash Controller
CPU Peripherals – VIC (Vectored Interrupt Controller), CRG11 (ClockReset Generator), IPCU (Inter-processorCommunication Unit), GPI0, Watchdog, Timer, MRBC (Remap and Boot Controller), SYSOC(System Operation Controller), SRAM on AXI (128KB), SRAM on AHB (64KB x2)
Bus Interconnect NIC-301 ARM Network Interconnect (AXI, AHB, APB)AHB BusMatrix AHB Interconnect
Others OPAL/RELC/ADC Instruction encryption/data compression and decompression / ADC 2ch for touch panel control
High-speed Cortex-A9 HLB (HierarchicalLayout Block)� 65nm: 600MHz� 40nm: 800MHz� 28nm: 1000MHz