Download - ePIXfab Technology and Partners
ePIXfab Joint Consortium Expertise
Amit Khanna
Coordinator, ePIXfab
Contents
• Introduction
– About IMEC, LETI and IHP
– ePIXfab Aim
– ePIXfab Users
• EU FP7 Support Action ESSenTIAL
• Services
– MPW
– Packaging and Integration
– Training and Support
imec
AT A GLANCE
4 © IMEC 2011 / CONFIDENTIAL
MISSION
▸ World-leading research in nano-electronics.
▸ Scientific knowledge with innovative power of global partnerships ICT, healthcare and energy.
▸ Industry-relevant technology solutions.
▸ International top talent in a unique high-tech environment committed to provide building blocks for a better life in a sustainable society.
Imec in the world
imec Belgium
imec The Netherlands
imec Taiwan
imec office Japan
imec office US imec China
imec India
5
IMECAMPUS
Total: 8000 m2 Clean Room 6
IMECAMPUS
Total: 8000 m2 Clean Room
Clean Room 2
3200 m2 Clean Room
300 mm pilot line, 65nm baseline
Ball Room, Clean sub-FAB
Continuous operation: 24hrs / 7 days
R&D on advanced CMOS
scaling
7
IMECAMPUS
Total: 8000 m2 Clean Room
R&D & Prototyping Facility
Heterogeneous Integration
Clean Room 1
4800m2 Clean Room
1750m2 Class 1
200mm pilot line, 130nm CMOS
Continuous operation:
24hrs / 7 days 8
CMORE 200mm Process capabilities
9 STEPHANE DONNAY JUNE 10, 2010
ASM 1100
Litho
• I-line, DUV, 193nm
• CD down to 50nm
DRIE
• high etch rate
• high aspect ratio
• angle capability
Centura platform
Low stress dielectrics
• SiO2, SiC, SiN
• Low temp SiO2
• Low stress <100MPa
Endura metal
Metals, plating
• Ti,TiN,Ta,TaN, AlCu, Cu, W ...
• Ni plating
• Compensation for low stress
SiGe, poly Si, c-Si
• c-Si low resistivity
• Poly-Si, SiGe
• Low stress and gradient
Release
PRIMAXX
• Dry HF release
• no stiction
• no residues
Suss XBC300HF
Wafer Bonding
• Anodic, Metal, polymers
and more
• Glass, Cu-Cu, Cu-Sn
9
In line defect monitor
• Defect detection &
classification
• Regular monitoring
KLA
CMORE ToolBox
Device Technologies
Packaging
Test
& R
elia
bili
ty
Embedded Systems, Design & Software
Multilayer Thin Film
3D TSV MEMS Capping Assembly
Digital Analog RF
System MEMS TCAD Modeling
Custom System Solutions V
V- Mp+Mp-
Mn+Mn-
MpBIAS
IBIAS
E
Wf
2
1
WWBar resonator
Electrical
Thermo-Mechanical
Defect Inspection
Materials Analysis
Optical
Environmental
SiGe HBT HV 24-600V
MEMS 130/90/65 nm CMOS
Si Photonics Novel Components
Imagers
ROIC
hybrid
diode
array
10
Silicon Photonics @Imec
Technology development for Optical chip-to-chip and chip-to-board Interconnect .
• Program with industry partners: Intel – Samsung – Panasonic – Fujitsu –
Roadmap for design and integration of passive and active modules
Dedicated project two application domains: Optical communication
(Bio)Sensors
IMEC’S Silicon photonics platform iSiPP vision for optical I/O
program
CPL
CW
LASER l2
SPL
CPL
CW
LASER l3
SPL
CPL
CW
LASER l4
SPL
CPL
CW
LASER l1
SPL
Photonics
M
CPLMOD l1MOD l2
MOD l3MOD l4
M
CPLMOD l1MOD l2
MOD l3MOD l4
M
CPLMOD l1MOD l2
MOD l3MOD l4
D
CPLDETDET
DETDET
D
CPLDETDET
DETDET
D
CPLDETDET
DETDET
Interconnect
waveguides
SE
RIA
LIZ
ER
Drivers
CMOS
Tra
nsm
it
l1 – l4
l1 – l4
l1 – l4
Drivers
Drivers
l1 – l4
l1 – l4
l1 – l4
Amplifiers
Amplifiers
Amplifiers
DE
SE
RIA
LIZ
ER
Receiv
e
Target = E-O/O-E transceivers
>1Tb/s @1pJ/bit
Co-integration of all electro-optical
components on a single opto-silicon
interposer platform
Optical I/Os for chip-to-chip and
chip-to-board interconnect
Relying on CMOS
fabrication technology:
ultra-compact
low-cost and power-efficient
p
nnn+
p+
p+n
+
SiN [100nm]
p+
Ge
Ge
n+
III-V
p+
Fiber Couplers
Passives
Waveguides Heaters
Photodetectors
c-Si
p-Si
c-Si
p-Si
Lasers
Modulators
p
nnn+
p+
p+n
+
SiN [100nm]
p+
Ge
Ge
n+
III-V
p+
Fiber Couplers
Passives
Waveguides Heaters
Photodetectors
c-Si
p-Si
c-Si
p-Si
Lasers
Modulators
Silicon photonics platform Technology roadmap
2011:
passive silicon
photonics platform
2012:
High-speed low-power
E-O modulators
2013:
Ge detectors
2014:
on-Si lasers
Many years of experience with
passive optical components:
waveguides, couplers, ...
2µm
First promising results on active
electro-optical components MRR modulators
III-V / silicon lasers 10Gb/s drivers
Ge photodetector
CMORE Turn your silicon Concept into a Product
Concept
Design
Process
development
Packaging
Testing
Reliability
Product
Qualification
Prototyping
Low-volume
manufacturing
@ imec
Transfer High-volume
manufacturing @ foundry partner
(Co-)development Prototyping Production
Silicon Photonics Technology Offering
Technology Exploration Development on Demand MPW R&D Runs
Offering Type Program-based (“CORE”), sharing results amongst all program partners
Project-based (“CMORE”), bilateral imec <-> customer
“ePIXfab”
Business offering
Deliverables Know-How and IP Prototype Chips and low volume manufacturing for commercial use
Proof of Concept Samples for R&D academic use
Know-How and IP Shared amongst partners without accounting
Bilateral sharing Dedicated clausules possible
No IP involved
Financials Program entrance fee Yearly partnership fee
Project (co)development cost Price per unit area and/or per wafer
Technology Exploration • Generic Platform Definition • Material, Device and Circuit Research • Device Models
Development on Demand • Design engineering • Platform tuning towards customer specifications • Dedicated fabrication runs • Specific add-on modules development
MPW R&D Runs • Shared fabrication runs • No design engineering • Best effort basis (schedule and performance)
Silicon Photonics Technology Offering
Technology Exploration Development on Demand MPW R&D Runs
Offering Type Program-based (“CORE”), sharing results amongst all program partners
Project-based (“CMORE”), bilateral imec <-> customer
“ePIXfab”
Technology Modules
Passive 2-level waveguides Available Available Available
Passive 4-level waveguides Available Available Available
Integrated Heaters Available Available 2012-2Q
Depletion Modulators Available Available 2012-3Q
MOS Modulators Available Available 2013
Ge Photo detectors Available 2012-2Q >2013
III-V-on-Si Bonding Available To be discussed Not planned
Laser Flip-Chip >2012-2H >2012-2H Not planned
Toolset (Wafer size) 130nm (200mm) 2012: 45nm (300mm)
130nm (200mm) 2013: 45nm (300mm))
130nm (200mm)
Technology Exploration • Generic Platform Definition • Material, Device and Circuit Research • Device Models
Development on Demand • Design engineering • Platform tuning towards customer specifications • Dedicated fabrication runs • Specific add-on modules development
MPW R&D Runs • Shared fabrication runs • No design engineering • Best effort basis (schedule and performance)
ABOUT LETI
300mm platform
300mm CMOS Integration
& adv. modules
Focus on advanced modules,
50 process equipments,
Strong in-line metrology,
Designed for short-loop with industry,
Advanced substrate development
200mm platform
300mm CMOS Integration
& adv. modules
200mm ‘CMOS’ new concepts
& Beyond CMOS
Full integration line for advanced devices,
SPC and in-line metrology,
Open to academia for scaling up new concepts,
Long practise of short-loop with industry.
BHT MEMS200 platform
300mm CMOS Integration
& adv. modules
200mm ‘CMOS’ new concepts
& Beyond CMOS More Than Moore 200mm
Integration with alternative materials (magnetic, OLED,
thick metals, molecular for biology, …)
Capacity for pilot line
Allocated capacity for key partners
State of the art 200mm microsystems equipments
All standard processes
• Deep RIE
• PVD, PECVD, RIE
• Litho tracks
• Semi automatic wet benches
Double sided ASML exposure with focus drill-down
Thick metal electroplating
New alloy material development (3 targets Cosputtering )
OLEDS deposition Cluster
Characterization platforms
300mm
CMOS Integration
& adv. modules
200mm
‘CMOS’ new concepts
& Beyond CMOS More Than Moore
200mm
Nanoscale
Characterization
Complete platform for morpho, chemical &
physical characterization,
Coupled with Synchrotron,
Open to services through SERMA
Nanocaracterisation about 50 tools:
Ion Beam, X ray, optical analysis etc…
A complete set of research platforms
From advanced concepts to pilot lines
Short loops with industrial sites
Cooperative with academia and industry
300mm CMOS Integration
& adv. modules
200mm ‘CMOS’ new concepts
& Beyond CMOS More Than Moore 200mm
Nanoscale Characterization
Exploratory Technology
Building 41
200&300mm wafers (FE)
We are here
The ePIXfab activivies on 200mm platform
Characterization
Facilities
Maintenance Process
Silicon Technology Platform and its « customers »
µelectronic
DTSi
Heterogeneous integration
Bio Optronic
More than Moore More Moore
Technological Interface
ABOUT IHP
ePIXfab
To establish access to silicon photonics technology for small scale users and emergence of a fab-less ecosystem
IC technology (Multi Project Wafers)
Packaging Training
ePIXfab is a collaboration between research institutes, coordinated by Imec
ePIXfab is supported by the EU (FP6, FP7)
2006 2012
Users
Industry
Research Institute
University
•Academic Research, biggest user group •Industry, evaluation of technology picking up
ESSenTIAL An EU FP7 Project supporting ePIXfab (2011-14)
ePIXfab services specifically targeting (SME) industrial take-up of advanced silicon photonics
Active Modules in Multi-Project Wafer Service Packaging and Integration Advanced Design kits & Support Training and Workshops Free Feasibility Studies for EU SMEs
Multi Project Wafers (MPW)
users
mask integration
send in design
fabrication
wafers distributed
Image ePIXfab website
MPW technology 2 layer Passive Technology
4 layer Passive Technology
Modulator Schematic Cross-sec, 2 level implants
Heater devices left, optical microscope. Right, SEM micrograph
Device cross-section after processing
Pieter Dumon IMEC confidential 2009 41
FC WG
SiO2
Si substrate
2000nm
220nm
70nm
Si
Top cladding
Pieter Dumon IMEC confidential 2009 42
70nm 1250nm
SiO2
Si substrate
2000nm
220nm 70nm
Si
5um
SiO2
Si substrate
2000nm
220nm
70nm
Si
1.25um planarized oxide 5um protective resist
Deep and shallow etch • Star coupler: shallow etch for less contrast
15µm 5µm
2µm
220nm
70nm
500nm
oxide
silicon
Performance, standard passives
Device Design Target Performance
Grating Coupler
315/315 FC layer, 25 periods
1550nm , TE 25-30 % coupling efficiency
Strip Waveguide
450X220 1550nm, TE Air clad- 2.5 dB/cm Oxide Clad-1.5dB/cm
44
Cross Section: Advanced passives
SiO2
Si substrate
Si
2000nm
220nm 70nm 220nm
150nm
Si
poly FC WG
FCW RFC
• 220nm + 380nm SOI in one design:
• 69% efficiency fiber couplers, ridge waveguides, ...
Performance, advanced passives
Device Design Target Performance
Grating Coupler
0.3/0.3 FC layer, 25 periods
1550nm , TE
60 % coupling efficiency
Modulators
Process
Lateral vs. interdigitated diodes design
Performances comparison
Outline:
Process
Lateral vs. interdigitated diodes design
Performance comparison
Process flow • Buried Oxide 2000nm (tBOX)
• Crystalline Si 220nm (tWG)
• Fiber Coupler height of 150nm (tFC)
Process flow • Pre-Metal Dielectric is 1000nm (tPMD)
• 1000nm (tPMD) is to avoid optical losses
• due to metal routing over waveguide
Process flow • Cu Metallization 600nm (tM1)
Process flow
BOX
Si
SiO2
N1 implanted Si
NPLUS implanted Si
PPLUS implanted Si
P1 implanted Si
NiSi
SiO2 PMD
W contact
SiO2 IMD
Cu metal 1
AlCu pads
tBOX
tWG tFC
tPMD
tM1
tPASS tPADtPAD
• Passivation 330nm (tPASS)
• Aluminium Pads
Outline:
Introduction
Process
Lateral vs. interdigitated diodes design
Performance comparison
Design of Lateral PN junction
-80 -40 0 40 80 120 160
2.5
3
3.5
4
d (nm)
n
eff (
10
-4)
-80 -40 0 40 80 120 1603
3.5
4
4.5
5
Op
tica
l lo
ss (
dB
/mm
)
Optical loss
neff
Oxide
P++ N ++
P+ impl N+ impl
d
Net doping distribution
N-type dopant distribution
P-type dopant distribution
6 V reverse bias
• waveguide width: 500 nm • waveguide height: 220 nm • slab height: 150 nm • doping concentration: 1e18 /cm3
w
N++ P++
P N
d
V∏L ∏ and Optical Loss dependence to “d”:
N region distance to P
-80 -40 0 40 80 120 1601.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
d (nm)
VL (
V·c
m)
-80 -40 0 40 80 120 1603.3
3.5
3.7
3.9
4.1
4.3
4.5
4.7
Optic
al l
oss
(dB
/mm
)
VL
Optical loss
Design of interdigitated PN junction
w
L= 1.6µm
0 1 2 3 4 5 60
1
2
3
4
5
Reverse Bias (V)
n
eff (10
-4)
w=250 nm
w=300 nm
w=400 nm
0 1 2 3 4 5 62.5
3
3.5
4
4.5
5
Reverse Bias (V)
Optical Loss (
dB
/mm
)
w=250 nm
w=300 nm
w=400 nm
1.4 µm
• VπLπ=0.62 V∙cm for a reverse bias of -1 V when w is 250 nm; • Reducing w can improving the modulation efficiency and cutting the loss;
Outline:
Introduction
Process
Lateral vs. interdigitated diodes design
Performance comparison
Comparison of two diodes in DC regime
0 1 2 3 4 5 60
1
2
3
4
Reverse Bias (V)
n
eff (10
-4)
0 1 2 3 4 5 61.1
1.5
1.9
2.3
2.7
Optical Loss (
dB
/mm
)
neff
: lateral PN
neff
: interdigitated PN
Loss: interdigitated PN
Loss: lateral PN
Lateral PN (1×1018/cm3)
Interdigitated PN (1×1018/cm3)
VπLπ at -1 V (V∙cm) 1.55 1.12
Loss at 0 V (dB/mm) 2.3 2.5
Capacitance at 0 V (fF/mm) 438 1590
0.1 0.2 0.5 1 2 5 10 20-55
-50
-45
-40
-35
-30
-25
Frequency (GHz)
|S21|2
(dB
)
0.5 mm
0.1 0.2 0.5 1 2 5 10 20-55
-50
-45
-40
-35
-30
Frequency (GHz)
|S21|2
(dB
)
1.5 mm
Frequency response and eye diagram of EO modulation
0.5 mm Interdigitated PN junction 1.5 mm lateral PN junction
Performance @ 10Gb/s Length (mm)
f3dB of |S21| at 0 (GHz)
Bias (V) Vpp (V) ER (dB) Power consumption
(pJ/bit)
Lateral PN junction 1.5 5.5 -1.5 2 8.5 0.47
Interdigitated PN junction 0.5 4.3 -2.5 3 7.5 1.25
• 10 Gbit/s • Vpp= 2 V • Bias=-1.5 V •PRBS: 215-1
• 10 Gbit/s • Vpp= 3 V • Bias=-2.5 V •PRBS: 215-1
f3dB of |S21| at 0 V: 4.3 GHz f3dB of |S21|2 at 0 V : 2.6 GHz
f3dB of |S21| at 0 V: 5.5 GHz f3dB of |S21|2 at 0 V: 3.6 GHz
Passive + heater MPW offer
A way towards closed loop operation
Thermal tuning efficiency depends on: Material volume to be heated Thermal coupling efficiency Expected time response Low power implies: Integration Scaling down active areas
THERMAL TUNING ELEMENT
Heaters
Output total 1
8
Input
E.G Resonator Ring with heater Ti TiN
1526 1528 1530 1532 1534 1536 1538 1540 1542 1544
0.00E+000
5.00E-008
1.00E-007
1.50E-007
2.00E-007
2.50E-007
3.00E-007
3.50E-007
4.00E-007
4.50E-007
5.00E-007
5.50E-007
6.00E-007
6.50E-007
7.00E-007
7.50E-007
8.00E-007
8.50E-007
9.00E-007
l=3nm/10mW Group B #8 P0mW
Group B #8 P2mW
Group B #8 P4mW
Group B #8 P6mW
Group B #8 P8mW
Group B #8 P10mW
Inte
nsity (
a. u
.)
Wavelength (nm)
E.g Heaters results hox=500nm, Q=13000 hox=600nm, Q=37000
The oxide thickness is fixed to 600nm, a compromise between optical losses generated by the Ti/TiN layer and thermal tuning efficiency.
Technology SOI wafer: Layer stack
220nm SOI / 2um BOX
Passive Process
Name of level Function
N° Mask Layer
Drawing grid en nm
Polarity
FC Fiber Coupler 01 1 Dark Field
WG Wave Guide 02 1 Light Field
HEAT HEATER 03 1 Light Field
SiO2 deposition 600nm
Ti/TiN Deposition
Litho of HEATER layer 03 CD min 120nm
CD control in the outer control border
Etch Ti/TiN
Stripping resist
CD control measurement
3 mask layers
Rules of critical dimension HEAT layer Values nm
Minimum width lines 120 nm
Minimum width spaces 250 nm
+
Heater module •Fc@ fixed dose @etching 70nm
•Minimum CD: 120nm
•WG @ sweep dose @etching 220nm
•Minimum CD: 120nm
•Heater @ fixed dose @etching 110nm
•Minimum CD: line 120nm space 250nm
SiO2
Si substrate
220nm
2000nm
70nm SiO2
WG FC Heater
MPW Lateral PiN Ge Photodetectors offer
• No gds available but
• Define a Pcell with a black box with defined optical connection RF connections We will add the gds file for PD cell during mask
integration Design Rule Manual Technological Document
Electrical PIN
11µm
12µm
Pin A
Pin K
0.5µm
Pin POPT
BlackBox Photodetector Optical PIN
Leti Ge PDs integrated at the end of the waveguide
Input waveguide
RF electrodes
10 µm Lateral PIN Ge diode
LETI CALL sign in
Passives + Photodetector
01/06/2012
MPW Standardized Photodetector
Leti offer MPW
-18
-15
-12
-9
-6
-3
0
3
0.1 1 10 100
AC
res
po
nse
(d
B)
frequency (GHz)
10E1
0V bias
0.5V bias
1.0V bias
2.0V bias
Sensitivity > 0.5A/W
Ge-on-Si lateral pin photodetectors of LETI
Epitaxy of germanium
G e
Si 1 µm
2.8 µm
G e
Si 50nm
M .D .
{111} S .F .
G e
Si 1 µm
2.8 µm
G e
Si 50nm50nm
M .D .
{111} S .F .
400°C / 750°C Growth + 5 x {890°C, 5 min. / 750°C, 5 min.} thermal cycling : promotes the glide of threading dislocations towards the substrat edges => TDD ~ 107 cm-2; tensily strained <= different dilat. coeff.
ECS Trans. 3, Vol. 7 (2006) 789
Low T /HighT cycle growth of Ge thick layers on
Si(001)
Centura RP-CVD Tool
Epi Centura :
- Mainframe
- Pumps
- Scrubber
(used gases)
- Gas cabinet
etc
Epitaxy Epitaxy
Pre-clean
Process gases :
- Carrier gas : H2
- SiGeC growth :
SiH4 , SiCH6 and GeH4
- Doping :
n : AsH3 and PH3
p : B2H6
- Selectivity :
SiH2Cl2 + HCl
Cool down -
wafer centering
Clean room wall
Reduced Pressure-Chemichal Vapour Deposition tool
Strained Ge absorption Absorption coefficient @ 1.3 µm (1.55 µm) : 10 000 cm-1 (4500 cm-1);
Direct band gap : 0.81 eV (bulk Ge) 0.78 eV (Ge/Si(001)) : tensile-strain.
Mask DUV 248nm minimum CD specifications
Follow the Design rules Manual for the specifications for each layers
And fill in the table of layers the minimum CD for your gds or each layer
Layer Acronym Description
Light
field or
Dark
field
Minimum
CD
Define others CD Control
alignment with
layer
Specification
s of of
overlays
1 FC Fiber coupler D (space 315nm) S400/L500/S400 none
2 WG Waveguide L (line 120nm) L400 2 on 1 +/-150nm
Photodetectors lithographies DUV 248nm
User 1
User 2
User 3
Block 1
Block 2
Block3
Block 4
Block 5
Block6
Mask Cost sharing different # users
Maximum design field for 248nm mask
rectangular 18.8 x 24.6 mm
Maximum 6 blocks
5 layers in DUV 248 to build PD ‘s devices
73
0.8 A/W ± 0.2 A/W at 1.55 µm
• Higher dark current / vertical
• Few µA @ -1V
• 30nA @ -0.1V
Lateral diode: DC characteristics
-18
-15
-12
-9
-6
-3
0
3
0.1 1 10 100
AC
res
po
nse
(d
B)
frequency (GHz)
10E1
0V bias 0.5V bias
1.0V bias 2.0V bias
Lateral diode: RF characteristics
• Clear dependency of the BW width implantation spacing
Parametric minimum performance targeted
• Parametrics performance at 1.55µm
Responsivity e.g >0.5A/W
Dark current < 3µA @ -0.5 V bias
Bandwith > 10GHz at -3dB in S21 @ -2V bias
Packaging & Integration for Silicon Photonics
laser collimation lens
isolator focusing lens
optical fibre
Fibre Coupled Semiconductor Lasers (high speed)
fibre in gripper
welded fibre
Assembly of Fibre in Butterfly Package (modified laser welding system)
Packaged 10G Burst Mode Receiver (SiGe BMRx chip on CPW)
Hybrid Integration (high speed photodiodes)
Mechanical Design of Laser Package (inset shows actual image)
Thermo-Mechanical Design of APD Array (APD array with integrated electronics)
Photonics Design (optical, mechanical, thermal)
Fibre Coupling to Silicon Waveguides
ePIXfab Silicon Photonics Workshop, April 2012.
output fibre
input fibre straight SOI waveguide
Fibre Coupling to Silicon Waveguides
ePIXfab Silicon Photonics Workshop, April 2012.
Input and Output Coupling to Straight Waveguides
1dB ± 2.5°
Fibre Coupling to Silicon Waveguides (tolerances)
3dB ± 5 mm
ePIXfab Silicon Photonics Workshop, April 2012.
packaged SOI ring resonator
Fibre Coupling to Silicon Waveguides (ePIXfab)
ePIXfab Silicon Photonics Workshop, April 2012.
Linear Planar Gratings
Inse
rtio
n L
oss
(d
B)
Wavelength (nm)
Fibre Coupling to Silicon Waveguides (ePIXfab)
ePIXfab Silicon Photonics Workshop, April 2012.
Ring Resonator (Device #3 / Die:-2,-2)
(peak transmission of -8.33dB)
Curved Planar Gratings
Inse
rtio
n L
oss
(d
B)
Wavelength (nm)
Fibre Coupling to Silicon Waveguides (modulators, ...)
ePIXfab Silicon Photonics Workshop, April 2012.
Si photonic chip (modulator)
electrical pins (not high speed)
standard fibre array block
angled Silica waveguide
Silicon platform (high density interconnect)
Fibre Coupling to Silicon Waveguides (future offering)
ePIXfab Silicon Photonics Workshop, April 2012.
tunable laser submount with grating coupling optics (submount can support high speed electronics)
ball lens & prism
tunable laser
flexible connector (3-sections for tuneable laser)
1,4 mm (AlN)
Active Device Integration on Silicon Photonics
ePIXfab Silicon Photonics Workshop, April 2012.
VTT
Design Kits Design Rule Manual
Manual describing the design rules necessary to follow for design acceptance at the fab
Technology handbook
Describes details of processing and performance characteristics of optical devices wherever available.
DRC deck
Using standard EDA tools (Mentor Graphics). Check the DRC errors yourself by running the DRC script
Sample gds files
Of typical block sizes, standard grating couplers, etc.
CAD software support
Design kits with technology decks, building blocks and p-cells are available in the following software
– PhoeniX (Imec, Leti)
– Ipkiss (Imec)
– PhotonDesign (under development)
– Cadence IC (Leti)
Training and Support 5-day training, 2/year
Program: • Technology
• Design rules
• Supply chain
• Procedures
• Hands-on design training (PhoeniX or Ipkiss)
1 day workshop, 1/year
Upcoming Workshop: ECOC, Amsterdam, Sep 2012
Upcoming training: April 2012, full
Next Training: November, 5-9, IHP Germany
Industrial Use
• Evaluation excercises
• MPW chips & packages
• Transfer to foundry services: – advanced prototyping
– development-on-demand
– low volume production
• Meet us near you
ePIXfab website
Contact Information
Address: ePIXfab IMEC-Ghent University
Dept. of Information Technology Sint-Pietersnieuwstraat 41, 9000 Gent, Belgium
Website: www.ePIXfab.eu Email: [email protected] Call: + +32-9-264 3324 Fax: +32-9-264 3593