EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Pei-Chen Chiu
On-behalf of the TPS Feedback Team
NSRRC, Hsinchu, Taiwan
Power Supply Control Interface and Orbit Feedback Environment
for TPS
2EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Outline
• TPS Power Supply & Control Interface• Integrated Orbit Feedback System Infrastructure• Corrector Control Interface • BPM & Feedback Engine Interface• Summary
EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Power Supply and Control Interface
4EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Storage Ring Dipole PS ParametersUnipolar TypeMaximum current 750 ANominal voltage rating 850 VCurrent control range 25-750 ACurrent Stability (100 s to 8 hours) ±10 ppm Award to IE PowerControl Interface Ethernet (similar with CLS)
Storage Ring Quadrupole PS ParametersUnipolar, switched-mode Maximum current rating 250 ANominal voltage rating 30 VCurrent control range 20-250 ACurrent Stability (0 to 8 hours) ±2.5 mA p-pContracted to Chroma ATE Inc Control Interface Ethernet (LXI compatible)
Storage Ring Power Supply (1/2)
5EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Storage Ring Sextupole PS Parameters(Include Transport line Magnet PS)Unipolar, switched-mode Maximum current rating 250 ANominal voltage rating 30 VCurrent control range 20-250 ACurrent Stability (0 ~ 8 hours) ±12.25 mA p-pContracted to Chroma ATE Inc Control Interface Ethernet (LXI compatible)
Storage Ring Power Supply (2/2)
6EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Booster Ring Power SupplyBooster Dipole PS ParametersQuadrant operation (Voltage bipolar, current unipolar)Typical waveform 3Hz biased sine waveMaximum peak current 1200 ANominal peak voltage(option1/2) + 1500 VCurrent control range 36-1200ACurrent Stability (100 s to 8 hours) ±10 ppmAward to IE PowerControl Interface Ethernet (similar as CLS)
Booster Quadrupole PS ParametersQuadrant operation (Voltage bipolar, current unipolar) Typical waveform 3Hz biased sine waveMaximum peak current 120 ANominal peak voltage(option1/2) + 425 VCurrent control range 1-120ACurrent Stability (100 s to 8 hours) ±10 ppmAward to IE PowerControl Interface Ethernet (similar as CLS)
7EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Storage Ring : Corrector, Skew Quad Power Supply Booster : Corrector, Sextupole Power Supply LTB, BTS : Corrector Power Supply
Corrector & BR Sextupole PS ParametersBipolar, switched-mode Maximum peak current ± 10 A Nominal peak voltage(option1/2) + 48 VCurrent control range -10~10ANoise level < 100 ACurrent Stability (0 ~ 8 hours) ± 100 A p-pManufactured by Industrial Technology Research InstituteControl Interface Analogue interface
Storage Ring Slow Corrector (± 600 rad) noise level < 5 nard (< 10 ppm)
8EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Interlock PLC IOC
EPICS IOCADLINK cPCI CPU
ADLINK 128 Bits DI/DO
TEWSTCP201
IP Carrier
Hytec IP ADC24 bits, 16 channels
IP-ADC-8417
EVR (CPCI6U-EVR-300)
Trigger Fanout
Trigger
Ramp Trigger
TPS Control Network
Hytec IP DAC18 bits, 16 channels
IP-DAC-8415
BR frev clock3 Hz
Power supplies trigger
EPICS IOCACQ164CPCI
24 bits ADC, 32 ch, GbE
SextupoleSD, SF PS
Ethernet Switch
Ethernet Interface:On/Off controlStatus readbackInterlock reset
Two Options: Analogue Reference Input (Waveform) or Embedded Waveform Generator
Booster Dipole, QF, Q1, Q2, QM PS (IE Power Inc.)
Booster Main Power Supply Control Interface
9EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
TPS Control network
CellPower Supply
Control cPCI IOC
Ethernet Switch
Quad (10), Sextupole (7)(Chroma ATE Inc.)
x 24
EPICS Access(10 Hz rate)
Orbit Feedback Setting(10 kHz rate)
CPU Module
±10 Amp Power Supplies (ITRI)
EVR (cPCI-EVR-300)
Corrector Power Supply
Controller(CPSC)
SR Slow Correctors 168 (H) +168 (V)SR Fast Correctors 96 (H) + 96 (V)
Skew Quadrupole 96BR Correctors 60 (H) + 36 (V)
EPICS IOC20 bits DAC24 bits ADC
(D-Tacq)
CLK/Trigger
Dipole PS(IE Power)
x 1
SR Power Supply Control in one Cell
EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Integrated Orbit Feedback System Infrastructure
11EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
TPS Slow and Fast Correctors for one Cell
Slow Correctors
Fast Correctors
CV/CH CV/CH CV/CH CV/ CH CV/CH CV/CH CV/CH
Boundary Conditions:Al Chamber (4 mm in thickness)7 BPM/cell (more will add in future)7 slow horizontal and 7 slow vertical corrector4 fast horizontal and 4 fast vertical corrector
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BPMArc BPM Straight BPM
(Primary BPM)Racetrack chamber
Courtesy by Vacuum Group
13EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Fast Correctors
Slow CorrectorsSR-SM (S4)
Winding on sextupole magnetsHorizontal 7 x 24 = 168Vertical 7 x 24 = 168
Horizontal 4 x 24 = 96Vertical 4 x 24 = 96
Mount on Bellows to achieve required bandwidth.
13
SR-SM (S3)
SR-SM (S2)
14EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
BPM electronic & IOFB module
Platform : Libera Brilliance+ Feedback Engine implemented in IOFB module
Grouping and IOFB module
15EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
SOFB at beginning, then FOFB later, running FOFB only! SOFB and FOFB running as two independent system with frequency dead-band. FOFB run from DC, a slow system receives the fast correctors from their DC part to prevent saturation.
SOFB
FOFB
FOFB
Orbit feedback system with combined fast and slow correctors
BPMs Fast control rules
Slow control rules
Fast corrector
AcceleratorResponse
Golden Orbit
Slow corrector
AcceleratorResponse
IOFB
SOFB + FOFB
FOFB Only FOFB
TPS Infrastructure for IOFB
16EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Required Elements for IOFB
• 7 x 24 BPM
• 7 x 24 slow horizontal corrector + 7 x 24 slow vertical corrector
• 4 x 24 fast horizontal corrector + 4 x 24 fast vertical corrector
• 2 x 24 IOFB modules (one for slow correction loop; one for fast correction loop)
• 3 x 24 CPSC modules (one for slow horizontal corrector interface; one for slow vertical corrector interface; one for fast horizontal and vertical corrector interface)
• Each cell (of 24 cells) should have 2 Brilliance+ platforms equipped with IOFB modules + 3 CPSC.
17EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
TPSControl System
Control Network Control Network
TPS Ring
Cell 13 CPSC s+ PSs
10 kHz rate interface. Each cell has 2 links.One for slow hor. and ver. loop.One for fast hor. and ver. loop
Power supply
EPICS CA
On-line modelingcomputer
Master Clock
Path length compensation
BPM Group 1
XBPM Electronics 1
XBPM Electronics n
BPM Group 2
XBPM Electronics 1
XBPM Electronics n
BPM platform 1IOFB module 1
BPM Group 24
XBPM Electronics1
XBPM Electronics m
Timing Master IOC
Rocket I/O grouping
link
BPM soft IOC
BPM platform 2IOFB module 2
BPM platform 1IOFB module 1
BPM pltform2IOFB module 2
BPM platform 1IOFB module 1
BPM platform 2IOFB module 2
Cell 23 CPSCs+ PSs
Cell 243 CPSCs+ PSs
Infrastructure
Related BPM ControlDiagnostic IOC
Group BPMOutput
18EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Simulated noise sensitivity function of the corrector VC014to bpm BPM011.
Simulation Results
3 dB B.W. ~ 500 Hz
BPMs slow corrector
Reference Orbit
Slow controllerΣs-1Us
T Vs
fast correctorFast controllerΣf-1Uf
T Vf
101
102
103
-30
-25
-20
-15
-10
-5
0
5
10
Am
plitu
de (
dB)
Frequency (Hz)
19EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
A Kick Change Simulation Results
Capability of OFB to suppress perturbation could be up to 20 dB for slower noise.
Corrections of fast correctors is almost less than plus/minus 0.05 urad at final, which is smaller than correction of slow correctors
0 10 20 30 40 50 60 70 800
2
4
6
Kic
k no
ise
(ra
d)
Time (msec)
0 10 20 30 40 50 60 70 80-1
-0.5
0
0.5
1
Ver
tical
BP
M p
ositi
on ( m
)
Time (msec)
0 10 20 30 40 50 60 70 80-2
-1
0
1
2
Fast corrector
Cor
rect
or ( r
ad)
0 10 20 30 40 50 60 70 80-2
-1
0
1
2
Slow corrector
Cor
rect
or ( r
ad)
Time (msec)
EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Corrector Control Interface
21EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Corrector Power Supply Interface
Analogue interface Choose 20 bits DAC Tested prototype
• Remote DAC setting (DAC installed at cPCI crate)
• Analogue sum (DC orbit correction + feedback compensation)
Difficult to achieve better than 17 bits performance. Thus, it decided to install the DAC/ADC as closed as power supply as possible.
DAC/ADC interface and PS put at the same crate.
22EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
0 100 200 300 400 500 600827.88
827.9
827.92
827.94
827.96
827.98
828
minute
(mV
)
10 hour test of 20bit DAC (AD5791)
(Full range +/- 6.6V)
6 count
23EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Temperature Effect on DAC output
0 100 200 300 400 500 60025
30
35
Tem
para
ture
0 100 200 300 400 500 600503.5
503.52
503.54
503.56
503.58
503.6
503.62
mV
Time (sec)
Chip Temp
Ambient Temp
5 change=> 80 uV drift℃16 uV(~1count)/ ℃
24EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Linearity test
12.6 uV step changeσ=0.047 uV(less than 0.01 count)
Each step: 1 count (~12.6 uV) settings
5 10 15 20 25 30 35 40 45 50 55
502.75
502.8
502.85
502.9
502.95
Time (sec)
mV
25EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
0 100 200 300 400 500 600 700 800 90010
-9
10-8
10-7
10-6
10-5
Frequency (Hz)
Volt
core area
6230
D-TACQ 18 bits DAC Module Output Test at Equipment Area Measurement
ComparisonIn the equipment site, it has more obvious power line noise.
0 10 20 30 40 50 60-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
Time (sec)
mV
core area
6230
1 count increasing
26EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
10-8
10-7
10-6
10-5
Frequency (Hz)
Vol
t
ao32
20bitDAC
D-TACQ AO32 18 bits DAC Module & 20 bits DAC Evaluation Module Output Comparison
27EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
50 100 150 200 250 300 350 400 450 50010
-7
10-6
10-5
10-4
10-3
10-2
Frequency (Hz)
Vol
t
ps reading
ao32
Use D-TACQ AO32 18 bits DAC Module Output as Reference Input of Power Supply Module
(Two separated rack, through 12m cabling)When connect to power supply, due to power-ground isolation, long-cabling induced noised and etc., the performance is deteriorated. The -80 dB noisy level is much higher than acceptable -106 dB.
1 mA (~ 60 nard)
100 A (~ 6 nard)
10 A (~ 0.6 nard)
28EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
20bit DAC Setting Power Supply TestInsert into PS crate slot 0
50 100 150 200 250 300 350 400 450 50010
-7
10-6
10-5
10-4
10-3
Frequency (Hz)
Vol
t
50 100 150 200 250 300 350 400 450 50010
-7
10-6
10-5
10-4
10-3
Frequency (Hz)
Vol
t
50 100 150 200 250 300 350 400 450 50010
-7
10-6
10-5
10-4
10-3
Frequency (Hz)
Vol
t
50 100 150 200 250 300 350 400 450 50010
-7
10-6
10-5
10-4
10-3
Frequency (Hz)
Vol
t
First modules Second modules
Reference
I monitor
10 A
100 A
1 mA (~ 60 nard)
10 A
100 A
1 mA (~ 60 nrad)
29EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Corrector Power Supply (± 10 A)
290 1 2 3 4 5 6 7 8 9 100
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
CURRENT AMPLITUDE ( A )
BA
ND
WID
TH
( H
z )
With Corrector magnet Load Current output Amplitude v.s.
Frequency
29
30EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Corrector Power Supply Controller (CPSC)
+
Slow SettingBuffer
External Clock (Up to 10 kHz Fast Setting Clock)
DO (LEMO connector, for timing measurement), Trigger out, Package received
Write Registers8 bit DO
Setting Buffers
GigabitEtherne
t
Slow Trigger(on demand, may not necessary)
Heartbeat Register
Rx
FastSetting Ports (GbE,
UDP/IP),Through
Port
Heartbeat Register
AURORA
8 Ch, 20 bit DAC
Single Board Computer(Linux, EPICS IOC) Status Registers
8 bit DI
24 ch, 16 bit ADC
8 ch, 24 bit ADC(10 kHz Sampling)
Slow Access(~ 10 Hz)
Control and Status
Registers
Ethernet Interface(Hardware UDP Stack)
96 pinDIN61412
Connectors x 2
+/- 15 V+ 5 V
4 ways,8 ch adder
~8 x 64 k x 32 bitWaveform Memory
Sequencer10 kHz clock
Waveform Memory
10 Hz rate data
Trigger (3 Hz) Precise digital temperature sensors
Individual Channel Enable/Disable?
10 kHz rate waveform
Control and Status Registers
Slow Access (~ 10 Hz)
Rx
Tx
FastSetting Port,
Through Port
(AURORA)
Tx
SFP Port
31EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Block Diagram of CPSC
IOFB correction
ID fast compensation
EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Feedback Engine Interface
33EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Requirement for IOFB modules1. Data Concentration of BPM data (X, Y, Sum, Status/Counter) and
support up to 256 BPM/pBPM. (utilize SFP1 & SFP2)2. Configurable 2 SFP output. (utilize SFP3 & SFP4)
• Output of grouped BPM/pBPM data via UDP/IP over GbE or customized AURORA protocol.
• Output of grouped magnet correction data via UDP/IP over GbE or customized AURORA protocol.
• Both of AURORA/GbE and BPM/magnet correction could be configured.
3. Inverse Response Matrix Calculation• Inverse matrix coefficient could be set by EPICS CA.• Corresponding magnet ID according to matrix could also be set by
EPICS CA. • Golden orbit set by EPICS CA too.
4. PI controller for different eigen-modes.5. 20 tap FIR.6. Trigger mechanism
34EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Infrastructure of IOFB modules
LVDS RX form 4*RAFs
LVDS TX to TIM
custom out
4*BPM dataSFP1
Grouping
???Orbit Data
(168 BPM, X and Y)
+Golden Orbit
(X and Y)
-
20 tap filters
n*PID controllers
On/Off
M(m*1) = R-1 * p (n*1)
dp
Magnet/BPMAURORA/GbE
Magnet/BPMAURORA/GbE
SFP2
SFP3
SFP4
Output Mapping?
Output Mapping?
35EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Interconnection within Cell’s CIATo Cell N-1
CPSC for slow horizontal corrector
7 CPSC for slow
vertical corrector7
CPSC for fast horizontal and vertical corrector
4 + 4
For diagnostic
Group 14*Magnet output
Group 8*Magnet output
Group 168*BPM output
repeater
Reserve for future expansion ( such as pBPM input?)
To Cell N+1
36EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
IOFB algorithm (1/2)• There are total 4 response matrix: sRx,sRy,fRx,fRy.• These four matrix will be decomposed by SVD. For example,
Slow horizontal response matrix 𝚼x=uxΣx vxT
• Therefore, inverse response 𝚼x-1=vxΣx
-1 uxT
• In order to do model space calculation, it is recommended that the IOFB modules should be allowed to download off-line the respective three elements: vx , Σ x
-1 , uxT
• Where uxT is 168*168 matirx(168 BPM), , Σ x
-1 is 168(or less than 168) array, and vx is also 168*168 matirx
• Since the IOFB is a kind of the distributed system, the calculation is also distributed. For example, for the 7 slow horizontal correction of the first cell. It is calculated as,
37EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
• Since TPS has 168 BPM and 168 slow correctors, there are 168 mode for slow loop in IOFB calculation and 96 mode for fast loop.
• For the 4 fast horizontal correction of the first cell. It is calculated as,
• The slow and fast loop would be calculate in two separate IOFB modules.
• For slow loop, it should know Ux(168*168) and Uy(168*168), Sx, Sy(each mode weights), 168 mode PID coefficient, and submatrix of Vx(7*168), Vy(7*168)
• For slow loop, it should know the first 96 mode of ux(96*168) and uy(96*168), sx, sy(each mode weights), 96 mode PID coefficient, and submatrix of vx(4*96), vy(4*96).
IOFB algorithm (2/2)
38EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Block diagram
UT V
AcceleratorBPM
Corrector
ReferenceOrbit
Measured Orbit+
Measured Noise
+
Orbit Disturbancedue to various sourcesOrbit
+
-
Response Matrix R = U* * VT
VacuumChamber
PID*-1
Slow loop:168*168Fast loop:96*168
Slow:168 Fast: 96
Slow:168*168 Fast: 96*96
IOFB coefficient
39EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Different size of response matrix calculation
168 168 168 168 168 168 168 168x x x xR U V
=
n
m
1. For the fast loop of the first cell, the IOFB should have 4 vertical fast magnet and 4 horizontal fast magnet .
2. For the slow loop of the first cell, the IOFB should have 7 vertical fast magnet and 7 horizontal fast magnet.
3. Support sizable matrix calculation or fixed to maximum configuration (unused part padded with zero).
40EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
BPM ID & Magnet ID
1. BPM ID: 1~1682. Magnet ID:
Beside IOFB, the global application is also considered. Ex, corrector response measurement, insertion device compensation.
Therefore, distinct Magnet ID is required for all correctors• 168*2+96*2=528• According to response matrix, output should be ordered
and assigned a magnet ID. Magnet ID number is depended on the, classified, location
and order. Such as,
1 0 11
0 1 1 1 0 1 1
Horizontal fast corrector 23th cell 3rd correctorMagnet ID
Format
41EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Summary Overview of TPS power supply control Feedback system infrastructure. BPM and corrector interface. Corrector power supply controller (CPSC) were
contracted to D-Tacq. I-Tech award the contract of BPM platforms. Specifications for integrated orbit feedback (IOFB)
FPGA modules are still on going. Communication between CPSC and IOFB modules
are in proceed now.
EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011
Thanks for Your Attention!