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EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsCircuitsCircuits
Lecture 8Lecture 8
EE141EECS141 1Lecture #8
Inverter Delay and PowerInverter Delay and Power
AnnouncementsAnnouncements
Homework #3 due todayHomework #4 posted today, due next FrMidterm1 Friday February 29 6:00-7:30pm
Open book
EE141EECS141 2Lecture #8
Will cover Lecture 1-8 (not including power)
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Class MaterialClass MaterialLast lecture
MOS capacitancesToday’s lecture
Inverter delayPower dissipation
EE141EECS141 3Lecture #8
Reading (3.3.2, 5.4, 5.5)
Simplified ModelSimplified ModelCapacitance models important for analysis and intuition
– But often need something simpler to work withSimpler model:
– Lump together as effective linear capacitance to (ac) ground
– In most processes: Cg = Cd = 1.5 – 2fF·W(µm)
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VoutVin
CL
VoutVin
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Review Review –– MOS CapacitancesMOS Capacitances
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The Miller EffectThe Miller Effect
Cgd1VoutΔV
As Vin increases, Vout drops – Once get into the transition region, gain
from V to V > 1Vin
M1
ΔVfrom Vin to Vout > 1
So, Cgd experiences voltage swing larger than Vin
– Which means you need to provide more charge
– Makes Cgd look larger than it really is
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Known as the “Miller Effect” in the analog world
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Review Review –– MOS CapacitancesMOS Capacitances
EE141EECS141 7Lecture #8
Review Review –– MOS CapacitancesMOS Capacitances
EE141EECS141 8Lecture #8
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Model CalibrationModel Calibration -- CapacitanceCapacitanceCan calculate Cg, Cd based on tech. parameters
But these models are simplified too– But these models are simplified tooAnother approach:
– Tune (e.g., in spice) the linear capacitance until it makes the simplified circuit match the real circuit
– Matching could be for delay, power, etc.
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CloadDelay1 Delay2Match
Model CalibrationModel Calibration for Delayfor DelayA
For gate capacitance:– Make inverter fanout 4 (will see why in 2 lectures)
Adjust C until Delay1 = Delay2
CloadDelay1 Delay2Match
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– Adjust Cload until Delay1 = Delay2For diffusion capacitance
– Replace inverter “A” with a diffusion capacitance load
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Delay CalibrationDelay Calibration1 4 16 64
Why did we need that last inverter stage?
Delay
"Edge Shaper" Load ???
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Propagation DelayPropagation Delay
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Transient ResponseTransient Response
1
1.5
2
2.5
Vou
t(V)
tpHL = ln(2) CL ReqntpLH = ln(2) CL Reqp
tpHLtpLH
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0 0.5 1 1.5 2 2.5
x 10-10
-0.5
0
0.5
t (sec)
( )1 1
2ln(2) 1
with '
=+
⎛ ⎞= − −⎜ ⎟
⎝ ⎠2
DDeq
DD DSAT
DS,effDSAT DD T DS,eff
VRλV I
VWI k V V VL
Delay as a function of VDelay as a function of VDDDD
( ) ( )L L
n n
= =− −
1 12 2 2
DD DDpHL
DSAT DD Tn DS,eff DS,eff
C V C VtI k' W L V V V V
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3.6
3.8x 10
-11
Device SizingDevice Sizing
(for fixed load)
2.6
2.8
3
3.2
3.4
3.6
t p(sec
)
( )
Self-loading effect:Intrinsic capacitancesdominate
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2 4 6 8 10 12 142
2.2
2.4
S
dominate
5x 10
-11
NMOS/PMOS ratioNMOS/PMOS ratio
4
4.5
t p(sec
)
tpLH tpHL
tp β = Wp/Wn
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1 1.5 2 2.5 3 3.5 4 4.5 53
3.5
β
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Step Inputs?Step Inputs?Derived RC model assuming input was a step
But input is not a stepBut input is not a step
Transistor turns on gradually
Let’s look at gate switching more carefullyUse our models to understand the effect of input slope
EE141EECS141 17Lecture #8
Use our models to understand the effect of input slope
Input Slope DependenceInput Slope Dependence
One way to analyze slope effect
outout L NMOS PMOS
dVI C I Idt
= = −
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Plug non-linear IV into diff. equation and solve…Simpler, approximate solution:
Use an approximate model (linear, piece-wise linear)
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Impact of Rise Time on DelayImpact of Rise Time on Delay0.35
t pH
L(ns
ec)
0.3
0.25
0.2
EE141EECS141 19Lecture #8
0.15
trise (nsec)10.80.60.40.20
tp = tstep(i) + ηtstep(i-1) (n ≈ 1/3)
CMOS Inverter CMOS Inverter Power DissipationPower Dissipation
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Where Does Power Go in CMOS?Where Does Power Go in CMOS?Switching power
Charging/discharging capacitorsCharging/discharging capacitorsLeakage power
Transistors are imperfect switchesShort-circuit power
Both pull-up and pull-down on during
EE141EECS141 21Lecture #8
Both pull up and pull down on during transition
Static currentsBiasing currents, in e.g. analog, memory
Dynamic Power ConsumptionDynamic Power ConsumptioniL 2
10 DDLVCE =→
VDD
( ) ( ) ∫∫ ∫DDVT T
VCdCVdttiVdttPE 2
Vin VoutCL
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( ) ( ) ∫∫ ∫ ====→ DDLoutLDDDDDDDD VCdvCVdttiVdttPE0
2
0 010
( ) ( ) ∫∫ ∫ ====DDV
DDLoutoutL
T T
LoutCC VCdvvCdttivdttPE0
2
0 0 21
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Dynamic Power ConsumptionDynamic Power Consumption2
10 DDLVCE =→
2
21
DDLR VCE =iL
VDD
One half of the energy from the supply is d i th ll t k h lf i
2Vin Vout
CL2
21
DDLC VCE =
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consumed in the pull-up network, one half is stored on CLEnergy from CL is dumped during the 1→0 transition
Circuits with Reduced SwingCircuits with Reduced Swing
( )
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( )0 1 L DDE C V V→ = Δ
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Dynamic Power ConsumptionDynamic Power ConsumptionPower = Energy/transition • Transition rate
C V 2 f= CLVDD2 • f0→1
= CLVDD2 • f • P0→1
= CswitchedVDD2 • f
EE141EECS141 25Lecture #8
Power dissipation is data dependent –depends on the switching probabilitySwitched capacitance Cswitched = CL • P0→1
Transition Activity and PowerTransition Activity and PowerEnergy consumed in N cycles, EN:
EN = CL • VDD2 • n0→1
n0→1 – number of 0→1 transitions in N cycles
fVCN
nfNEP DDLN
NNavg ⋅⋅⋅⎟
⎠⎞
⎜⎝⎛=⋅= →
∞→∞→
210limlim
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NN ⎠⎝0 1
0 1 limN
nN
α →→ →∞
=
fVCP DDLavg ⋅⋅⋅= →2
10α
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Short Circuit CurrentShort Circuit CurrentVDD
Isc ∼ 0
VDD
Isc = IMAX
1
1.5
2
2.5
I sc (A
)
x 10−4
CL = 20 fF
CL = 100 fF
C = 500 fF
VinVout
CLVin
Vout
CL
Large load Small load
EE141EECS141 27Lecture #8Short circuit current usually well controlled
0 20−0.5
0
0.5
40 60
I CL = 500 fF
time (s)
Transistor LeakageTransistor LeakageTransistors that are supposed to be off -leak
VDD 0V
VDD
ILeak
VDD0V
VDD
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Input at VDD Input at 0
ILeak
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Diode LeakageDiode Leakage
GATE
Np+ p+
Reverse Leakage Current
+
-Vdd
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JS = 10-100 pA/μm2 at 25 deg C for 0.25μm CMOSJS doubles for every 9 deg C!Much smaller than transistor leakage in deep submicron
IDL = JS × A
Transistor LeakageTransistor Leakage
-4
-3
VDS = 1.2V
G
-8
-7
-6
-5
log
I DS
[log
A]
G
S D
Sub
Ci
Cd
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-90 0.2 0.4 0.6 0.8 1 1.2
V GS [V]
Drain leakage current is exponential with VGS-VT
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SubSub--Threshold ConductionThreshold Conduction10
-2
Li
Inverse Subthreshold Slope:( )GS Tq V V C−
10-8
10-6
10-4
I D(A
)
Linear
E ti l
Quadratic
( )
0~ , 1 DnkTD
ox
CI I e nC
= +
S-1 is ΔVGS for ID2/ID1 =10
-1
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0 0.5 1 1.5 2 2.510
-12
10-10
VGS (V)
VT
Exponential
Typical values for S-1:60 .. 100 mV/decade
Transistor LeakageTransistor Leakage
3-10x in current
technologiesI DS
[nA]
( )( )
0 1GS T DS DSq V V V qV
nkT kTDI I e e
η− −−⎛ ⎞
= −⎜ ⎟⎝ ⎠
EE141EECS141 32Lecture #832
Two effects:• diffusion current (like a bipolar transistor)• exponential increase with VDS (η: DIBL)
00 0.2 0.4 0.6 0.8 1 1.2 1.4
V dS [V]
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Threshold VariationsThreshold VariationsVTVT
L
Long-channel threshold Low VDS threshold
VDS
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L
Threshold as a function of the length (for low VDS)
Drain-induced barrier lowering (DIBL) (for short L)
Next LectureNext LectureBuffer sizing
EE141EECS141 34Lecture #8