DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRS
ASDEN Methodology, Capabilities, and Demonstration
2nd Quarter, 2000JRS Research Laboratories
Motorola
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRS
Presentation Overview
Design Methodology
Current Capabilities
JRS Fill-in-the-gap Tool Developments
Demonstration Scenario
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRSASDEN Design Process
Reusable SoftwarePrimitives, Graphs(application & OS),
Test Vectors,Device Drivers
HW Architectures &Components
(boards, chips,cores & peripherals)
HW/SWCharacterization
Data (performanceformulas: timing,power, memory)
Off-line ModelBuilding
ProjectPlanning &
Management
System Application Functional Modeling
Functional Simulation/Debugging, HW-in-the-loop Verification
ReactiveControlCapture
Data FlowGraph
Capture
StateDiagramCapture
AlgorithmExploration
Architecture Selection (HW/SW CoDesign)
Trade-offs, Cost Estimates
PerformanceAnalysis
Assignments& Mappings
Trade-OffMatrix
Establish & Evaluate Requirements
RequirementsData
RequirementsTracking
Platform Implementation & Software
Emulation Calibration
Mixed-LevelSimulation
HWDevelopment
Kit
Diagnostics& Analysis
Budgets: cost, Size,Functionality,Reliability
Functional applications,Functional data, Test vectors
Assignment list, HW/SW parts,Schedules, OS calls
SystemDesign Data
Sets
Trade-off DataSets
ValidationData Sets
Parts list,Test vectors,Cal. maps
Code Generation
System
Driver APIs, RTOS,
BootstrappingLoad Modules, Load Scripts, HW Init
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRSDesign Methodology Instantiation
ASDEN long-term goals: Support all automotive electronic design arena process flows Support engineers’ tools-of-choice within each domain Support numerous existing platforms (microcontrollers, RTOS’, S/W
architectures) Support what if tradeoffs and performance analyses for new platform designs
ASDEN Current Targets: Engine Electronic Control Unit design arena Series of tools supporting crucial end-to-end processes Motorola’s best-in-class offerings in HW & OS slated for the automotive sector Precursor to hypothetical designs using performance analysis estimating tool Requirements, experimentation, and test vector management (flow down)
Current Tool Set P ro jec t M anagem ent
M A T LA B &M A T R IX x B locks ,
E C U A pp l.(O S : M ot. O S E K ),
S P S D rive rs
B lackO ak ,TP U 3 & D P R A M , ,
R IM 2 ,R 2 I,Q S M C M ,TO U C A N ,
Q S M , M IO S I,O AD C 64 , U S IU , U IM B ,
L2U , B urs t B u ffe r,Q A D C , M IO S E ven t
S ched
A na lys is , P E R T sC harac te r iza tionD ata (S P S M ode lC ha rac te r iza tion )
O ffline M ode lB u ild ing
P aperlessE ng ineering
N o tebook
S ys te m A pp lica tion F unc tiona l M ode ling
F u nctiona l D es ign /S im u latio n /D ebu gg ing : M A T R IX x o r M A T L A B
M A T R IX xD ata F low
G raphC ap tu re
S ta teD iagramC ap tu re
M A T LA B
A rch itec tu re S e lec tion (H W /S W C odes ign)
T rade-o ffs : A S D E N A na lys is : C o re & per iphe ra lC os t E s tim a tes : T rade -o ff M a trix
A na lys is &A ss ignm e nt,
P E R T s ,C us tom
E stab lish , E va lua te , & F ilte r D ow n R equ ire m en ts
JR S P ape rlessE ng ineering N o tebo ok
B udge ts : cos t, S izeF unctio na lity , T es tS e ts , R eliab ility
F unc tiona l app lica tions ,F unc tiona l da ta , T es t vec to rs
A ss ignm en t lis t, H W /S W parts ,S chedu les, O S ca lls
P arts lis t,T est vec to rs ,C a l. m a ps
S ys temD es ign D ata
S e ts
T rade-o ff D a taS e ts
V a lida tionD a ta S e ts
T rade -O ffM a trix
Load M o du les,Load S crip ts ,B oo ts trap
E m u la tio n C a lib ra tion
S D S s im /debu gge r, E V B s, Log ic A na lyzers , S ig G e ns
S D SD eb ugger
M ot. E V BD eve lopm e nt
K it
C a lib ra tionT oo ls
P la tfo rm Im p lem enta tion & S o ftw a re
C G S , H L A P I,I/O D rive rs
O S E K O S ,H W
In itia liza tion
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRSTool Integrations -- ASDEN Framework
Cohesive tool launcher
Reusable Libraries User workspace and file
management Internal semantic models
provide tool transitions
•Integrated System Inc.’s MATRIXx•The MathWorks MATLAB•Software Development Systems (SDS)’ SingleStep Simulator/Debugger•Diab Data’s compilation tool suite•Univ. of Illinois / JRS PERTS performance analyzer•Motorola’s OSEK V2.0•Motorola’s OSEK Sysgen and Builder•Motorola’s MPC555 EV Board developers kit•Motorola’s PSD I/O Drivers for Ford•JRS peripheral device analyzers (3)•JRS system designs Tradeoff Matrix•JRS Paperless Engineering Notebook (PEN)
•System application models•Hardware cores & peripherals•Real-time operating systems•Design arena domain APIs•I/O Drivers•Platforms•Tools
Current Tool List
Libraries
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRSJRS Fill-in-the-gap Tool Developments
System performance analyzer (PERTS) Code Generation/Synthesis System (CGS) Paperless Engineering Notebook (PEN) HW peripheral (I/O Devices) analysis packages
Devices: QADC64, TPU3, MIOS
Tool integrations >> The all-important glue.
•MATRIXx / MATLAB >> generic application description format (ADF)
•ADF >> PERTS
•ADF >> CGS
•ADF >> Peripheral Analyses
•ADF >> RTOS Library (OSEK Sysgen)
•ADF >> I/O Driver Library
•System Libraries >> tools, GUI
•PERTS >> Tradeoff Matrix
•CGS >> Diab tool suite
•CGS >> SDS SingleStep Debugger
•SDS >> Motorola EVB
•HW test bench >> EVB >> HW test bench
•PEN >> MATLAB >> PEN
•PEN >> Performance Analysis >> PEN
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRSDemonstration Scenario
Intro to ASDEN and PEN features
Current tools are mixture of full functional and conceptual capabilities.
End-to-end run
6-8 tools to reflect methodology flow
Data objects:
4 cylinder ECU spark & fuel strategy
Motorola PowerPC for automotive sector (MPC555)
Motorola Real-time operating system (OSEKOS)
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSPEN and ASDEN Scenario Interactions
PENRequirements
Page
PENSimulation
Page
PENImplementation
Page
PENTPU Analysis
Page
ASDENSystem
Modeling
ASDENCode Synthesis
System
ASDENTarget
Validation
Documentation
Matlab Executable Spec
Test Vectors
Sim. Results
Wire Harness Report
Test Vectors (voltages)
Real-time Results
Real-time Results
Expected Results
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSASDEN Main Panel -- Process Flow
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSFeatures -- Library Browsers
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSFeatures -- Compiler Options
Compilation Tools for embedded microcontrollers are extremely complex, as a rule.
•Diab Data’s compiler, assembler, and linker have over 200 options.
•The slightest tweak on a compiler command line can have drastic performance and memory effects.
•ASDEN uses 3 separate configurations for I/O drivers, operating system, and application code compilations.
• ASDEN provides recommended defaults.
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSStep 1: Executable Requirements Modeling
Reusable strategy with ASDEN high level API
ASDEN-provided MATLAB and MATRIXx palette of engine control input/output blocks.
Enables ease of model development and retargetable code generation.
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSStep1: ASDEN Simulink Processing Builds Upon the
MATLAB Environment
TestHarnessModel
ModelControl Block GUI
IO BlockLibrary
MDLFile
RTW File
Tasking info for CGS targetspecific code generation
RTW C Sourcefor Applicationfunctional code
ASDEN TLC
SimulinkLibrary
Standard TLC
ASDENm-file Model Manipulation
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRSStep1: Modeling Paradigm Helps to Structure
Application Designs for Test and ValidationApplication model is constructed within a testing harness
A Subsystem is designated by the user to be the applicationSurrounding blocks are assumed to be part of the test harnessAn ASDEN Model Control Block manages this relationship
All model IO is performed by ASDEN IO blocksFor Simulation, the model is structured such that
Data is passed into the Sensor block inputs as raw ‘voltage’ signals Actuator block actions may be monitored on their output ports, which
pass the data values sent to underlying actuator driver callsFor code generation purposes, sensors and actuators become data
sources and sinks Sensors obtain data directly; their inputs effectively disappear Actuators do not output values; the driver calls terminate the data
flow
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRSStep2: Validate Strategy against Requirements
Utilize JRS Paperless Engineering Notebook
ASDEN example includes pages for:
ECU requirements documentation
Strategy Test Plan Validation through
simulation Integrated Simulink
simulation launch and data extraction
Validation through implementation (EVB execution)
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSStep 3: System Design Configuration
User’s must configure reusable library elements in order to create new system designs.
•Compiler Options
•Application Model
•Platform Model
•System Mapping
Target Definitions provide a basket for all necessary data to get embedded s/w running on target platforms automatically. They support configuration management and requirements traceability.
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSStep4: Performance Analysis
Analysis Refers to Schedulability of Processing Automotive applications are more generally categorized as Real-Time
systems
System correctness depends on valid computations, but also that they are
done in time, or the system has failed
Processors and smart peripherals have processing assigned to them or tasks
to perform Many MPC555 peripherals have micro-schedulers and kernels that make them CPUs in
their own right
The idiosyncrasies of the peripherals require custom analysis
The basic issue to analyze is whether the interaction of the core and
peripheral tasks will allow them to meet application timing deadlines
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSStep4: Performance Analysis (cont)
ASDEN Support of the Spark/Fuel Strategy Identified Core and Peripherals Needs
MATRIXx and MATLAB models enhanced to use ASDEN I/O blocks I/O blocks handle sensor inputs and actuator outputs
Provides functional processing, e.g. convert sensor voltage to engineering units
Provides tie-in to peripherals and SW drivers Mapping to candidate peripherals on the MPC555
QADC64 for analog to digital conversion of inputs
TPU3 for event monitoring and actuator control
Core processor for functional model execution
Generated code divided into angle and time driven tasks
RMA based techniques used to form analysis of peripherals and core
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSStep 4: System Performance Analysis & Estimation
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRS
Step 5: TPU3 Peripheral Analysis & Programming
The TPU is a highly programmable peripheral Provides users with a great deal of flexibility At the same time, lots of decisions with little guidance on how to apply or setup
the device for an application
Two key elements allow ASDEN processing to automatically program the TPU3 Definition of an application SW Architecture or usage model in which to apply the
device This provides some of the device settings in the form of SW drivers
Worst Case Latency (WCL) based Analysis provides key to determine the rest The remaining device parameters are determined by analyzing the operation of
the device from an Rate Monotonic Analysis (RMA) point of view
Relationships between the channel processing are set to guarantee meeting application deadline requirements
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRS
Step 6: Automatic Code & Load Module Synthesis
User must identify the following inputs:•High level behavioral requirements model•High level API implementation•I/O Driver Library•Retargetable platform selection•Platform-specific initializations & optimizations•Compilation options
Output: Production-intent full implementation software load modules.
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JRSCode Generation System: Execution Model
Fuel Control Spark Control OBD
ECT
OSEK Scheduler
Sync
Eng PosISR
System TimerISR
ECT Sensor
MAPSensor
Tasks
ISRs
MAP SetSpark
10deg
100ms
…
… …GlobalVariables
Events
High Level API
Low Level API
SparkControl
Hardware peripheral devices: TPU, QADC, ...
ECTISR
MAPISR
Eng PosSensor
SensorsActuators …
Configuration Commands Interrupts
FuelControl
INIT
ASDEN AngleEvent Scheduler
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRS CGS: Reusable Strategy Key -- High Level
API
Removes system designer from microcontroller-dependent implementation details
Independent of microcontroller and peripheral hardware, but dependent on specific
sensor/actuator components.
Intended to provide a complete interface between the application functionality and the
hardware.
Enables ability to Bridge the Gap automatically
Pure system level design to production-intent implementation
User interface is a predefined library of API function blocks used to build the application
model.
Used in same manner as libraries supplied by tool vendor.
Initial implementation is for both MATLAB and MATRIXx; portable to other tools.
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
Confidential Proprietary
JRS
CGS: High Level API (continued)
Implementation of API utilizes I/O driver low level API provided by Motorola’s
Powertrain Systems Division
JRS created an initial version of a High Level API for use in ASDEN.
Defines functions such as:
float Get_ECT(); /* Get engine coolant temperature in degrees C */
float Get_TP(); /* Get throttle position as percent of full throttle */
status Set_Spark(float stop_angle, float dwell, int cyl); /* Set spark */
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSStep7: Real-Time Verification
M PC555
Scope / LogicAnalyzer
S ignal/FunctionG enerator
Application Tasks(MATRIXx)
HL APIIm plem entationsPSD I/O Drivers
CG S SystemTasks
Mot. OSEKO S
Bootstrap
DigitalDNA Systems Architecture Laboratory / PSD / Global Software Division
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JRSDemonstration Summary
What are we going to see?
4-cylinder spark & fuel strategy modeled in both MATRIXx and MATLAB
Test vector requirements management and flow down for simulation and
implementation
Strategy evaluated on several platforms via a Performance Analyzer
Automatically generated production-intent implementation
Motorola PowerPC 555, OSEK 2.0 operating system
Real-time execution of the code on an evaluation board