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Lecture 6 : Desi n Mar inReliabilit and Scalin
CSCE 6730Advanced VLSI Systems
Instructor: Saraju P. Mohanty, Ph. D.
NOTE: The figures, text etc included in slides are borrowed, , ,sources for academic purpose only. The instructor doesnot claim any originality.
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Lecture Outline
Design Margin upp y o age, empera ure, rocess ar a on, e c.
Reliability Electromigration, Self-heating, Hot-carriers, etc.
Transistors, Interconnect, etc.
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Design Margin
Three different sources of variation: nv ronmen a
Supply voltage pera ng empera ure
Manufacturing
Process variation Variations can be modeled as uniform or
Gaussian distribution.
Ob ective: Desi n a circuit that o erates reliableover extreme ranges of the above variations.
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Design Margin : Supply Voltage
ICs are designed to operate at nominal supply.
Supply voltage may vary due to: rop L di/dt noise (self inductance)
M di/dt noise (mutual inductance) The delay in a device (td) that determines the
maximum frequency (fmax) or the clock cycle time
(T) isTd= kVdd/ (Vdd-Vth). Here, kand aretechnology dependent constants.
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Design Margin : Temperature Sensitivity
Increasing temperature
Reduces Vth
ON ecreases w empera ure
IOFFincreases with temperature
dsI
increasingtemperature
Vgs
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Design Margin : Parameter Variation
Transistors have uncertainty in parameters eff, th, ox Vary around typical (T) values
fas
t
FF
as
Leff:short OS TT
SF
Vth: low tox: thin
p
slow SS
FS
Slow (S): opposite
Not all arameters are inde endentnMOS
fastslow
for nMOS and pMOS
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Design Margin : Environmental Variation
VDDand T also vary in time and space
:
VDD:high : ow
Corner Voltage Temperature
.
T 1.8 V 70CS 1.62 V 125C
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Design Margin : Corners
Process corners describe worst case variations ,
for any variation.
, ,
NMOS speed
spee Voltage
empera ure
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Design Margin : Important Corners
Some critical simulation corners include
DD
Cycle time S S S S
Power F F F FSubthrehold F F F S
leakage
Pseudo-NMOS S F ? ?
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Reliability
Designing reliable CMOS chips are essential.
MTBF = (#devices * Hrs of Operation) / # Failures
Failures in Time FIT : The number of failures thatwould occur every thousand hours per million devices,i.e. 109 * (failure rate / hour).
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Reliability : Electromigration
Electromigration decreases reliability.
e e u e e y.
Occurs in wires carrying DC rather than AC, asin DC the electrons flow in a same direction.
Mean Time to Failure :
MTF exp(Ea/kT) / Jndc, a
determined) and nis constant (=2).
materials, severe for aluminum than copper.
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Reliability : Electromigration
For electromigration we need a lot of electrons,.
Electromigration does not typically occur in
semiconductors, but may in some very heavilydoped semiconductor materials.
Electromigration can lead to either open circuit or
s or c rcu a ure.
Open circuit failure Hillocking, short circuit failure
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Source: http://www.csl.mete.metu.edu.tr/Electromigration/emig.htm
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Reliability : Self-heating
Typically bidirectional signal lines RMS (root-
heating.
el -heating may cause temperature-inducedelectromigration problems in bidirectional signal
lines. Self-heating is more prominent for SOI processes
because of poor thermal conductivity of SiO2.
RMS current is calculated as:
Irms= (I(t)2dt / T)
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Reliability : Self-heating and Electromigration
density limit the
operation. DC current: problem in
power and ground lines
bidirectional signal lines
Solution: widenin thelines or reducing the
transistor sizes,.
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Reliability : Hot Carriers
High-energy (hot) carriers get injected into the.
The damaged oxide change the IV characteristics:
e uce curren n
Increases current in PMOS
Hot carriers may cause circuit wearout as NMOStransistors become too slow.
Negative bias temperature instability (NBTI) is an
similar mechanism in PMOS, where holes aretrapped in oxide.
Refer:htt ://www.semiconfareast.com/hotcarriers.htm
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Reliability : Latch-up
.
In addition an NPN and an PNP transistor formed
-NMOS, p-type substrate and n-well.
Substrate and well provide resistance
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Reliability : Latch-up
When parasitic BJT formed by the substrate,well and diffusion turn ON then latch-u occurs.
This can lead to a low-resistance path between
su l and round. With proper process advances and layout
consideration this can be avoided
Rsuband Rwellneed to be minimized (guard rings)
-parasitic BJT.
to latch-up (
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Reliability : Over-voltage Failure
Over-voltage problem due to :
Oxide breakdown
Time dependent dielectric breakdown (TDDB) of gate
Electrostatic discharge (ESD): static electricity
Punchthrough: Higher voltages applied betweensource an ra n ea to punc t roug w enthe source/drain depletion regions touch.
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Reliability : Soft Errors DRAM occasionally flip value spontaneously. A soft error
will not damage a system's hardware; the only damage isto the data that is bein rocessed.
There are two types of soft errors:
Chip-level soft error: Occurs when the radioactive'particles into the chip. The particle can hit a DRAM celland change it state to a different value.
System-level soft error: Occurs when the data beingprocessed is hit with a noise phenomenon, typicallywhen the data is on a data bus. The com uter tries tointerpret the noise as a data bit, which can causeerrors in addressing or processing program code. Thebad data bit can even be saved in memor and causeproblems at a later time.
When the corrupt bit is rewritten it is equal likely to.
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ource: p: www.we ope a.com so _error. m
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Why?
Why more transistors per IC?
Larger dice
y as er compu ers
Smaller, faster transistors
Better microarchitecture (more IPC) Fewer gate delays per cycle
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Scaling : Assumptions
What changes between technology nodes? e
All dimensions (x, y, z => W, L, tox
)
o age DD Doping levels
Lateral Scaling Only gate length L
Often done as a quick gate shrink (S = 1.05)
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Scaling : Influence on MOS device
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Scaling : Observations
Gate capacitance per micron is nearly
But ON resistance * micron improves with
Gates get faster with scaling (good)
Dynamic power goes down with scaling (good) Current densit oes u with scalin bad
Velocity saturation makes lateral scaling
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Scaling : Example
Gate capacitance is typically about 2 fF/m e ve e e y e e
process of feature size f(in nm) is about 0.5fps
Estimate the ON resistance of a unit (4/2 )transistor.
FO4 = 5= 15 RC
RC = (0.5f) / 15 = (f/30) ps/nm
, .
Unit resistance is roughly independent of f
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Interconnect Scaling : Assumptions
Wire thickness .
Wire length
oca sca e n erconnec
Global interconnect e s ze sca e y
c
.
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I S li I fl
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Interconnect Scaling : Influence
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I t t S li Ob ti
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Interconnect Scaling : Observations
Capacitance per micron is remaining constant .
Roughly 1/10 of gate capacitance
oca w res are ge ng as er
Not quite tracking transistor improvement
But not a major problem Global wires are getting slower
No longer possible to cross chip in one cycle
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International Technology Roadmap for
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International Technology Roadmap for
em con uc ors
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S li I li ti
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Scaling Implications
Improved Performance ve
Interconnect Woes Power Woes
Productivit Challen es
Physical Limits
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S li I li ti C t I t
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Scaling Implications : Cost Improvement
In 2003, $0.01 bought you 100,000 transistors
Moore03
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Scaling Implications : Reachable Radius
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Scaling Implications : Reachable Radius
We cant send a signal across a large fast chip
But the microarchitect can plan around this
us as o -c p memory a enc es were o era e
Chip size
Scaling of
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Scaling Implications : Dynamic Power
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Scaling Implications : Dynamic Power
Intel VP Patrick Gelsinger (ISSCC 2001) , ,
speed processors would have power density of
nuclear reactor b 2010 a rocket nozzle and b2015, surface of sun.
Business as usual will not work in the future.
Intel stock dropped 8%
But attention to power isincreasing
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oore
Scaling Implications : Static Power
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Scaling Implications : Static Power
VDDdecreases
Protect thin gate oxides and short channels
.
Vthmust decrease to
maintain device performance But this causes ex onential Dynamic
increase in OFF leakageStatic
Moore03
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Scaling Implications : Productivity
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Scaling Implications : Productivity
Transistor count is increasing faster than
Bigger design teams
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More expensive design cost
Rely on synthesis, IP blocks
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Scaling Implications : Physical Limits
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Scaling Implications : Physical Limits
Will Moores Law run out of steam?
Cant build transistors smaller than an atom
Many reasons have been predicted for end ofscaling
Dynamic power
Subthreshold leakage, tunneling Short channel effects
Fabrication costs
Electromi ration Interconnect delay
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