Download - Design Flow Enhancements for DNA Arrays
Design Flow Enhancements for DNA Arrays
Andrew B. Kahng1 Ion I. Mandoiu2 Sherief Reda1 Xu Xu1 Alex Zelikovsky3
(1) CSE Department, University of California at San Diego(2) CSE Department, University of Connecticut(3) CS Department, Georgia State University
Introduction to DNA microarrays and manufacturing challenges
Outline
DNA microarray design flowDNA microarray design flow enhancements:
Integration of Probe Placement and EmbeddingIntegration of Probe Selection and Physical Design
Conclusions and future research directions
Uses of DNA arrays
Introduction to DNA microarrays
Practical experiment using DNA arrays
DNA manufacturing process
Problems and challenges in DNA manufacturing process
Introduction to DNA Probe ArraysDNA Arrays (Gene Chips) used in wide range of genomic analyses
gene expression detectiondrug discoverymutation detection
Diverse fields from health care to environmental sciences
DNA Arrays are composed of probes where each probe is a sequence of 25 nucleotides
Images courtesy of Affymetrix.
Tagged RNA fragments flushed over array Laser activation of fluorescent tags
Optical scanning of hybridization intensities
DNA Array Hybridization Experiment
DNA Array Manufacturing Process
Very Large-Scale Immobilized Polymer Synthesis (VLSIPS)
Treat substrate with chemically protected linker molecules
Selectively expose array sites to light
Flush chip’s surface with solution of protected A, C, G, T
Repeat last two steps until desired probes are synthesized
Probe Synthesis
array probes
A 3×3 array
CG AC G
AC ACG AG
CG AG CN
ucle
otid
e D
epos
ition
Seq
uenc
e A
CG
A Mask 1
A
A
A
A
A
Probe Synthesis
array probes
A 3×3 array
CG AC G
AC ACG AG
CG AG CN
ucle
otid
e D
epos
ition
Seq
uenc
e A
CG
C Mask 2
CC
C C
C
CA
A
A
A
A
Probe Synthesis
array probes
A 3×3 array
CG AC G
AC ACG AG
CG AG CN
ucle
otid
e D
epos
ition
Seq
uenc
e A
CG
G Mask 3
CC
C C
C
CA
A
A
A
A
G
G GG
GG
A Nucleotide Deposition Sequence defines the order of nucleotide deposition
A Probe Embedding specifies the steps it uses in the nucleotide sequence to get synthesized
VLSIPS Manufacturing Challenges
Lamp
Mask
Array
Problem: Diffraction, internal reflection, scattering, internal illumination
Occurs at sites near to intentionally exposed sitesReduce interference
Increase yield
Reduce cost
Design objective: Minimize the border length
Unwanted Illumination and Border Cost
array probes
A 3×3 array
CG AC G
AC ACG AG
CG AG CN
ucle
otid
e D
epos
ition
Seq
uenc
e A
CG
A Mask 1
A
A
A
A
A
Border = 8
Border Reduction
Unwanted illumination Chip’s yield
Introduction to DNA arrays manufacturing challenges
Outline
DNA array design flowDNA array design flow enhancements:
Integration of Probe Placement and EmbeddingIntegration of Probe Selection and Physical Design
Conclusions
Previous Work
Border minimization was first introduced by Feldman and Pevzner. “Gray Code masks for sequencing by hybridization,” Genomics, 1994, pp. 233-235
Work by Hannenhalli et al. gave heuristics for the placement problem by using a TSP formulation.
Kahng et al. “Border length minimization in DNA Array Design,” WABI02, suggested constructive methods for placement and embedding
Kahng et al. “Engineering a Scalable Placement Heuristic for DNA Probe Arrays ,” RECOMB03, suggested scalable placement improvement and embedding techniques
Basic DNA Array Design Flow
Probe Selection
Design of Test Probes
Probe Placement
Probe Embedding
DNA Array
Logic Synthesis
BIST and DFT
Placement
Routing
VLSI Chip
Physical Design
Probe Placement
Probe Embedding
Probe Selection
Design of Test Probes
Logic Synthesis
BIST and DFT
Physical Design
Routing
Placement
Analogy
Design Flow Outline
Physical Design
Degrees of freedom (DOF) in probe embedding DOF exploitation for border conflict reduction
Probe Embedding
Probe Placement Similar probes should be placed close together
Constructive placement Placement improvement operators
Key DOF: Probe Embedding (Alignment)
A
A
A
C
C
C
G
G
GT
T
T
Deposition Sequence
CTG
Hypothetical Probe
Gro
up
C
G
T
Synchronous Embedding
C
T
G
As Soon As Possible (ASAP)
Embedding
C
G
T
Another Embedding
Embedding Determines Border Conflicts
A
A
A
C
C
C
T
T
TG
G
G
ACTG
AGT
GTG
A A
Synchronous EmbeddingA
G
T
A
G
G
T
A
Dep
ositi
on S
eque
nce
ProbesG
A
A
G
T
A
G
T
ASAP Embedding
G
Optimal Probe Embedding
T
A
AG
A
G
T
A
C
A
T
G
Before optimal re-embedding
A
T
A
AG
G
T
A
C
A
T
G
After optimal re-embedding
A
Using Dynamic Programming to optimally re-embed a probe
Problem: Optimally embedding a probe with respect to its neighbors
Kahng et al. “Border Length Minimization in DNA Array Design,” WABI02
AAAAAA
Placement Polishing Using Re-Embedding
Use optimal re-embedding algorithm to re-embed each probe with respect to its neighbors
Placement Objective: Minimize Border
Radix-sort the probes in lexicographical order
Probe 1
Probe 2
Probe 3
Probe 4
Probe 5
T A T T
A T A A
A A C A
G GC C
C G G G
1 2 3 25
T A T T
A T A A
A A C A
G GC C
C G G G
1 2 3 25
Problem: How to place the 1-D ordering of probes onto the 2-D chip?
Radix-sorting the probes order reduces discrepancies between adjacent probes
Placement By Threading
1 2 3 25
T A T T
A T A A
A A C A
G GC C
C G G G
Probe 1
Probe 2
Probe 3
Probe 4
Probe 5
Thread on the chip
1
2 3
4 5
Row-Epitaxial Placement Improvement
Array of size 4 × 4
For each site position (i, j):From within the next k rows, find the best probe to place in (i, j) Move the best probe to (i, j) and lock it in this position
Row placement = sort + thread + row epitaxial
Introduction to DNA arrays manufacturing challenges
Outline
DNA array design flowDNA array design flow enhancements:
Integration of Probe Placement and EmbeddingIntegration of Probe Selection and Physical Design
Conclusions
DNA array design flow enhancements
Integration of Probe Placement and Embedding
Integration of Probe Selection and Physical Design
Initial embeddings influence the placement results
Propose and implement two flows
Probe pools add additional degrees of freedom Integrate probe selection into physical design
Propose and implement two flows incorporating probe pools
Physical Design
Probe Selection
Design of Test Probes
Probe Placement
Probe Embedding
DNA Array
Integration of Probe Placement and Embedding
Probe Selection
Design of Test Probes
Probe Placement
Probe Embedding
DNA Array
Integrating placement and probe embedding gives a further reduction in border conflicts.
Probe Placement
Probe Embedding
Analogous to tighter integration between placement and routing in VLSI physical design
Integration of Probe Placement and Embedding
1. Synchronous initial embedding
3. Re-embedding using DP2. Row placement
Flow A
Row EpitaxialRe-embedding
ASAP initial embedding1. As Soon As Possible (ASAP) initial embedding
3. Re-embedding using DP2. Row placement
Flow B
010002000300040005000600070008000900010000
100 200 300 500 Chip size
Conflicts
6%
Placement + Embedding Runtimes
Row EpitaxialRe-embedding
0
2000
4000
6000
8000
10000
12000
100 200 300 500 Chip size
CPU (s)
1. Synchronous initial embedding
3. Re-embedding using DP2. Row placement
Flow A
Row EpitaxialRe-embedding
ASAP initial embedding1. As Soon As Possible (ASAP) initial embedding
3. Re-embedding using DP2. Row placement
Flow B
Second Enhancement: Probe Pools
Probe Selection
Design of Test Probes
Probe Placement
Probe Embedding
DNA Array
Physical Design Problem: Given a probe pool
for every target sequence, select a probe for every target sequence such that the total conflict after placement and alignment is minimum.
Probe 1 Probe 2 Probe 3 Probe 4
Gene Target Sequence
Probe Pool – Pool Size = 4
Integrating Probe Selection and Physical Design
1. Perform ASAP embedding of all probe candidates
3. Re-embedding
2. Run row placement selecting the probe from the pool that gives the minimum conflict
Flow A
ASAP initial embedding1. Perform ASAP embedding of all probe candidates
3. Run row placement using the selected candidates
2. From each probe pool select the probe that fits in the least number of steps using ASAP
Flow B
4. Re-embedding
Results (Conflicts) of Probe Pools
300000310000320000330000340000350000360000370000380000390000
1 2 4 8 16
Chip size = 100
Pool Size
Conflicts
2600000
2700000
2800000
2900000
3000000
3100000
3200000
3300000
1 2 4 8 16
Chip size = 300
Pool Size
Conflicts
8000000
8100000
8200000
8300000
8400000
8500000
8600000
8700000
1 2 4 8 16
Chip size = 500
Pool Size
Conflicts
1150000
1200000
1250000
1300000
1350000
1400000
1450000
1500000
1 2 4 8 16
Chip size = 200
Pool Size
Conflicts
Comparison of Probe Pools Flows
300310320330340350360370380390
1 2 4 8 16
Chip size = 100
Pool Size
Conflicts
2600
2700
2800
2900
3000
3100
3200
3300
1 2 4 8 16
Chip size = 300
Pool Size
Conflicts
68007000720074007600780080008200840086008800
1 2 4 8 16
Chip size = 500
Pool Size
Conflicts
1150
1200
1250
1300
1350
1400
1450
1500
1 2 4 8 16
Chip size = 200
Pool Size
Conflicts
Results (runtime) of Probe Pools
0
1
2
3
4
5
6
7
8
1 2 4 8 16
Chip size = 100
Pool Size
CPU (1000s)
0102030405060708090100
1 2 4 8 16
Chip size = 300
Pool Size
CPU (1000s)
020406080100120140160180
1 2 4 8 16
Chip size = 500
Pool Size
CPU (1000s)
051015202530354045
1 2 4 8 16
Chip size = 200
Pool Size
CPU (1000s)
Interpretation and Summary of Experimental Data
Initial ASAP embeddings produce a decent reduction in border conflicts.
Probe pools offer an extra degree of freedom exploited to further reduce border conflicts
Integration of placement and embedding yield up to 6% improvement
Probe pools add an extra 12-13% improvement
Total improvement up to 18% compared to results published in the literature
Open Research Directions
Probe selection should incorporate ability to uniquely detect target sequences present in sample. This should be done with no ambiguity. Methods similar to Boolean covering and test diagnosis can be used.
P1 P2 P3 P4 P5
T1
T2
T3
T4
Each target sequence should have a unique signature
Probes
Target Sequences
Open Research Directions
Stronger placement operators leading to further reduction in the border cost.
Insertion of probe test can benefit from test and diagnosis topics for VLSI circuits.
Future work also covers next generation chips 10k × 10k
Conclusions
We presented a DNA design flow benefiting from experiences of the VLSI design flow
We introduced feedback loops and integrated a number of steps for further reduction in the border cost and hence unwanted illumination
We examined the effects of probe selection on both placement and embedding
We examined the embedding options and placement on the total border cost
Thanks for your attention