Defect-Aware Design Paradigm for Reconfigurable Architectures
Rahul Jain, Anindita Mukherjee, Kolin PaulIndian Institute of Technology, Delhi
Conference Travel Supported by XILINX-CMC, Hydrabad, India
IntroductionVLSI Technology progress for finer dimensions and larger chip area has lead to:
More Complex Fabrication TechniquesHigh defect densitiesHigh Manufacturing Costs
Decrease in Critical Defect SizeIncrease in defect/fault-sourcing complexity factorLower Yield
Milton Godwin et al, “Examining upcoming yield enhancement challenges in the 2001 roadmap”, Micro Magazine, 2002 Issue
IntroductionLow Yield problem can be overcome by
Fault ToleranceDefect Tolerance
This Relaxes Stringent Constraints on Manufacturing Processes
Lowers CostA tradeoff between process technology complexity in terms of yield and post-fabrication complexity in terms of defect-tolerance
MotivationDefect-tolerance more important as we near lithographic limitsWe are moving towards era of molecular electronicsCAEN- Chemically assembled electronic nanotechnology
Expected to have about 10% defectsReconfigurable Devices (e.g. FPGA’s) obvious choice to incorporate post-fabrication defect-tolerance
Area PenaltyTime Penalty
Defect Aware Design Flow
FPGA used as the Reconfigurable FabricPnR now expects a Defect Map as inputObservations:
Interconnect defects are the bottleneck as they occupy the most areaDefect Distribution is clustered [C. H. Stapper 89]
Congestion Aware Placement gives best Results
Experimental Setup
VPR used as the FPGA PnR infrastructureplacement and routing tool for array-based FPGAs from University of Toronto
VPR modified to accept Defect Map as inputDefects mapped to CLBs and interconnectsDefective components assigned ZERO capacity, hence cannot be used in PnR
Motivational Example
Conducted to Study the PnR behaviour for different Defect DensitiesUniform Random Defect distribution for CLB’sand Routing Resources (RR) assumedExpected Behaviour:
Placement always possible if enough defect-free CLB’s availableAs we increase the defect density of RR the circuit gets unroutable
Motivational ExampleObserved Behavior
Expected behavior most of the timeBut some cases where Circuit is routable for Higher CLB defects with same or even Higher RR defectsReason for this is that at Higher CLB defects the Placement is more distributed and hence no/less congestion
ConclusionArea Penalty InevitablePlacement is more distributive hence Time Penalty incurredCongestion Awareness needed at the Placement Step
Defect Map Generation
Simulation Model by C.H Stapper usedModel takes chip as a 2D Grid ArrayUses a Symmetrical Bivariate Gaussian DistributionCluster Shaping done on this DistributionClusters randomly Rotated and Displaced
Mapping Defects on FPGA Fabric
FPGA Fabric divided into a 2-D Array of cells of side equal to interconnect widthInterconnect modeled as 1-D Array of cellsCLB modeled as 2-D array of cellsDefect Map Generated for this FPGA 2D-ArrayIf any defect maps to any Resource, Assign Zero capacity to the Resource
VPR Cost Functions
Experiment Conducted to find the best PnRmethodology in Defect Aware EnvironmentVPR uses Simulated Annealing for Placement and Path_Finder Algorithm for routing4 types of Placement Cost Functions
Bounding Box with Linear Cost function (BB_L)Bounding Box with Non-Linear Cost function (BB_NL)Net_timing_driven (Net)Path_timing_ driven (Path)
VPR Cost Functions
NANANA8.55721apex1
NANA8.148.071122table5
6.06.288.327.581127table3
NANANA5.571123scf
NANA5.495.70615gcd
pathNetBB_LBB_NL
T_Crit (10-8 s)chanwdnx/nyBench
Comparison of 4 Cost Functions
RISA
Bounding Box, Non Linear Algorithm gives the best resultsIt is an implementation of cost-function RISA [Cheng, ICCAD’94]
RISA balances demand and supply over an array of NxN regionsRISA performs better than others because it is congestion awareRISA takes routability into account while doing placement
RISA
Demand:
Supply:
NTS vijv /= NTS hijh /=
WX
lwqD
LY
lwqD verti
k
horizi
k ×
××=
×
××= ,, ;
Chih-Liang Eric Cheng, “RISA: accurate and efficient placement routability modeling”, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
CA-RISA
Supply reduced due to defectsPenalize defects with a weighing factor WLarge value of W pushes the placements away from highly defective regions
vdefi j
vijv NWNTS ∑∑−= */
hdefi j
hijh NWNTS ∑∑−= */
A Defective FPGA Fabric
Scf Benchmark
CLB’s = 418
nx/ny = 26
chan_wd = 16
% Def CLB’s = 2.7
% Def Int. = 9.8
Placement by RISA
Congestion Map for RISA Placement
Placement by CA-RISA
Routable /
Zero Congestion
Base Cases- Defect Free Environment
4542761.12e-071522alu4
4225001.10e-071064ex5p
2209008.55e-08700apex1
1616048.07e-08485table5
1482257.57e-08480table3
784005.57e-08418scf
345965.70e-08220gcd
Total AreaT_CritCLBBench
Base Cost
Current Design Methodology
61012.617.63.21522alu4
4629.215.52.81064ex5p
3692.515.82.4700apex1
246-4.412.63.7485table5
25120.111.01.9480table3
38239.67.41.3418scf
19252.514.22.5220gcd
AreaTimeintclb
Penalty (%)Defect (%)No.ofCLB's
Bench
Defective Fabric
Performance Evaluation of CA-RISA
8.06104.317.63.2alu4
1.84627.315.52.8ex5p
5.45369-3.115.82.4apex1
2.33248-6.612.01.8table5
15.792511.111.01.9table3
22.153828.67.41.3scf
4.5019245.614.22.5gcd
AreaTimeintclb% Imp
% Penalty%Def Bench
Least Time Penalty
Performance Evaluation of CA-RISA
10.455316.518.32.8alu4
5.843726.514.92.3ex5p
6.1934024.19.81.5apex1
13.4220015.613.92.9table5
20.4418014.612.14.0table3
8.5934130.19.82.7scf
019245.614.22.5gcd
AreaTimeintclb%Imp
% Penalty%Def Bench
Least Area Penalty
RISA vs CA-RISA
05783142alu4
003243alu4
3413243235ex5p
014663334ex5p
26692531apex1
05912630apex1
07382026table5
06922125table5
102801824table3
03731925table3
05781626scf
001726scf
001217gcd
CA-RISARISA
Congestionchan_wdnx,nyBench
Future Work
Proposed Methodology requires the circuit to be Placed and Routed for Each Chip SeparatelyNot a Feasible OptionIncorporate Defect Map into the Flow as late as possibleOne Possibility is to do PnR for non-defective fabric and at the last step incrementally map the solution to the defective fabric
Conclusion
CA-RISA proposed and compared to existing methodologyThis is not a Complete Solution A motivation for Defect Aware Design ParadigmTries to highlight the bottlenecks of the Present Methodology
Thank You
Questions