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Contents
Cortex-A Series Programmers Guide
PrefaceReferences ....................................................................................................................... x
Typographical conventions .............................................................................................. xi
Feedback ........................................................................................................................ xii
Terms and Abbreviations ............................................................................................... xiii
Chapter 1 Introduction1.1 History ........................................................................................................................... 1-3
1.2 System-on-Chip (SoC) .................................................................................................. 1-4
1.3 Embedded systems ...................................................................................................... 1-5
Chapter 2 The ARM Architecture2.1 Architecture versions .................................................................................................... 2-3
2.2 Architecture history and extensions .............................................................................. 2-4
2.3 Key points of the ARM Cortex-A series architecture .................................................... 2-8
2.4 Processors and pipelines .............................................................................................. 2-9
Chapter 3 Tools, Operating Systems and Boards3.1 Linux distributions ......................................................................................................... 3-2
3.2 Useful tools ................................................................................................................... 3-6
3.3 Software toolchains for ARM processors ...................................................................... 3-8
3.4 ARM DS-5 ................................................................................................................... 3-11
3.5 Example platforms ...................................................................................................... 3-13
Chapter 4 ARM Registers, Modes and Instruction Sets4.1 Instruction sets .............................................................................................................. 4-2
4.2 Modes ........................................................................................................................... 4-3
4.3 Registers ....................................................................................................................... 4-4
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4.4 Instruction pipelines ...................................................................................................... 4-7
4.5 Branch prediction ........................................................................................................ 4-10
Chapter 5 Introduction to Assembly Language5.1 Comparison with other assembly languages ................................................................ 5-2
5.2 Instruction sets .............................................................................................................. 5-4
5.3 ARM tools assembly language ..................................................................................... 5-5
5.4 Introduction to the GNU Assembler .............................................................................. 5-75.5 Interworking ................................................................................................................ 5-11
5.6 Identifying assembly code .......................................................................................... 5-12
Chapter 6 ARM/Thumb Unified Assembly Language Instructions6.1 Instruction set basics .................................................................................................... 6-2
6.2 Data processing operations .......................................................................................... 6-6
6.3 Multiplication operations ............................................................................................... 6-9
6.4 Memory instructions .................................................................................................... 6-10
6.5 Branches ..................................................................................................................... 6-13
6.6 Integer SIMD instructions ........................................................................................... 6-14
6.7 Saturating arithmetic ................................................................................................... 6-18
6.8 Miscellaneous instructions .......................................................................................... 6-19
Chapter 7 Caches7.1 Why do caches help? ................................................................................................... 7-3
7.2 Cache drawbacks ......................................................................................................... 7-4
7.3 Memory hierarchy ......................................................................................................... 7-5
7.4 Cache terminology ........................................................................................................ 7-6
7.5 Cache architecture ........................................................................................................ 7-7
7.6 Cache controller ............................................................................................................ 7-8
7.7 Direct mapped caches .................................................................................................. 7-9
7.8 Set associative caches ............................................................................................... 7-11
7.9 A real-life example ...................................................................................................... 7-12
7.10 Virtual and physical tags and indexes ........................................................................ 7-13
7.11 Cache policies ............................................................................................................ 7-14
7.12 Allocation policy .......................................................................................................... 7-15
7.13 Replacement policy .................................................................................................... 7-167.14 Write policy ................................................................................................................. 7-17
7.15 Write and Fetch buffers .............................................................................................. 7-18
7.16 Cache performance and hit rate ................................................................................. 7-19
7.17 Invalidating and cleaning cache memory .................................................................... 7-20
7.18 Cache lockdown ......................................................................................................... 7-21
7.19 Level 2 cache controller .............................................................................................. 7-22
7.20 Point of coherency and unification .............................................................................. 7-23
7.21 Parity and ECC in caches ........................................................................................... 7-24
7.22 Tightly coupled memory .............................................................................................. 7-25
Chapter 8 Memory Management Unit8.1 Virtual memory .............................................................................................................. 8-3
8.2 Level 1 page tables ....................................................................................................... 8-48.3 Level 2 page tables ....................................................................................................... 8-7
8.4 The Translation Lookaside Buffer ................................................................................. 8-9
8.5 TLB coherency ............................................................................................................ 8-10
8.6 Choice of page sizes .................................................................................................. 8-11
8.7 Memory attributes ....................................................................................................... 8-12
8.8 Multi-tasking and OS usage of page tables ................................................................ 8-15
8.9 ARM Linux use of page tables .................................................................................... 8-18
Chapter 9 Memory Ordering9.1 ARM memory ordering model ....................................................................................... 9-4
9.2 Memory barriers ............................................................................................................ 9-6
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9.3 Cache coherency implications .................................................................................... 9-11
Chapter 10 Exception Handling10.1 Types of exception ...................................................................................................... 10-2
10.2 Entering an exception handler .................................................................................... 10-4
10.3 Exit from an exception handler ................................................................................... 10-5
10.4 Exception mode summary .......................................................................................... 10-6
10.5 Vector table ................................................................................................................. 10-810.6 Distinction between FIQ and IRQ ............................................................................... 10-9
10.7 Return instruction ...................................................................................................... 10-10
Chapter 11 Interrupt Handling11.1 External interrupt requests .......................................................................................... 11-2
11.2 The Generic Interrupt Controller ................................................................................. 11-5
Chapter 12 Other Exception Handlers12.1 Abort handler .............................................................................................................. 12-2
12.2 Undefined instruction handling ................................................................................... 12-4
12.3 SVC exception handling ............................................................................................. 12-5
12.4 ARM Linux exception program flow ............................................................................ 12-6
Chapter 13 Boot Code13.1 Booting a bare-metal system ...................................................................................... 13-2
13.2 Configuration .............................................................................................................. 13-6
13.3 Booting Linux .............................................................................................................. 13-7
Chapter 14 Porting14.1 Endianness ................................................................................................................. 14-2
14.2 Alignment .................................................................................................................... 14-6
14.3 Miscellaneous C porting issues .................................................................................. 14-8
14.4 Porting ARM assembly code to ARMv7 .................................................................... 14-11
14.5 Porting ARM code to Thumb .................................................................................... 14-12
Chapter 15 Application Binary Interfaces15.1 Procedure call standard .............................................................................................. 15-2
15.2 Mixing C and assembly code ...................................................................................... 15-7
Chapter 16 Profiling16.1 Profiler output ............................................................................................................. 16-3
Chapter 17 Optimizing Code to Run on the ARM Processor17.1 Compiler optimizations ............................................................................................... 17-3
17.2 ARM Memory system optimization ............................................................................. 17-7
17.3 Source code modifications ........................................................................................ 17-13
17.4 Micro-architecture optimizations ............................................................................... 17-18
Chapter 18 Floating Point18.1 Floating-Point Basics and the IEEE-754 Standard ..................................................... 18-2
18.2 VFP Support in GCC .................................................................................................. 18-9
18.3 VFP support in the ARM Compiler ............................................................................ 18-10
18.4 VFP Support in Linux ................................................................................................ 18-11
18.5 Floating point optimization ........................................................................................ 18-12
Chapter 19 Introducing NEON19.1 SIMD ........................................................................................................................... 19-2
19.2 NEON architecture overview ...................................................................................... 19-3
19.3 NEON comparisons with other SIMD solutions ........................................................ 19-10
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Chapter 20 Writing NEON Code20.1 NEON C compiler and assembler ............................................................................... 20-2
20.2 Optimizing NEON assembler code ............................................................................. 20-6
20.3 NEON power saving ................................................................................................... 20-9
Chapter 21 Power Management21.1 Power and clocking ..................................................................................................... 21-2
Chapter 22 Introduction to Multi-processing22.1 Multi-processing ARM systems .................................................................................. 22-3
22.2 Symmetric multi-processing ........................................................................................ 22-6
22.3 Asymmetric multi-processing ...................................................................................... 22-8
Chapter 23 SMP Architectural Considerations23.1 Cache coherency ........................................................................................................ 23-2
23.2 TLB and cache maintenance broadcast ..................................................................... 23-4
23.3 Handling interrupts in an SMP system ........................................................................ 23-5
23.4 Exclusive accesses ..................................................................................................... 23-6
23.5 Booting SMP systems ................................................................................................. 23-9
23.6 Private memory region .............................................................................................. 23-11
Chapter 24 Parallelizing Software24.1 Decomposition methods ............................................................................................. 24-2
24.2 Threading models ....................................................................................................... 24-4
24.3 Threading libraries ...................................................................................................... 24-5
24.4 Synchronization mechanisms in the Linux kernel ....................................................... 24-8
Chapter 25 Issues with Parallelizing Software25.1 Thread safety and reentrancy ..................................................................................... 25-2
25.2 Performance issues .................................................................................................... 25-3
25.3 Profiling in SMP systems ............................................................................................ 25-5
Chapter 26 Security
26.1 TrustZone hardware architecture ................................................................................ 26-2
Chapter 27 Debug27.1 ARM debug hardware ................................................................................................. 27-2
27.2 ARM trace hardware ................................................................................................... 27-3
27.3 Debug monitor ............................................................................................................ 27-6
27.4 Debugging Linux applications ..................................................................................... 27-7
27.5 ARM tools supporting debug and trace ...................................................................... 27-8
Appendix A Instruction SummaryA.1 Instruction Summary ..................................................................................................... A-2
Appendix B NEON and VFP Instruction SummaryB.1 NEON general data processing instructions ................................................................. B-6
B.2 NEON shift instructions ............................................................................................... B-12
B.3 NEON logical and compare operations ...................................................................... B-16
B.4 NEON arithmetic instructions ...................................................................................... B-22
B.5 NEON multiply instructions ......................................................................................... B-30
B.6 NEON load and store element and structure instructions ........................................... B-33
B.7 VFP instructions .......................................................................................................... B-39
B.8 NEON and VFP pseudo-instructions .......................................................................... B-45
Appendix C Building ARM LinuxC.1 Building the Linux kernel ............................................................................................... C-2
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C.2 Creating the Linux filesystem ........................................................................................ C-6
C.3 Putting it together .......................................................................................................... C-8
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Preface
This book is intended to provide an introduction to programmers using processors which conform
to the ARM ARMv7A architecture. (The v7 refers to version 7 of the architecture, while A
indicates the architecture profile that describes Application Processors.) This includes the
Cortex-A8, Cortex-A9 and Cortex-A5 processors. It is intended to complement the official
documentation, such as the ARM Technical Reference Manuals(TRMs) for the processors
themselves, documentation for individual devices or boards and of course, most importantly. for all
ARM programmers, the ARMArchitecture Reference Manual(or the ARM ARM). This book
does not seek to replace any of these sources of information. Although much of the text is also
applicable to other ARM processors, we do not explicitly cover processors that implement older
versions of the Architecture, or those that fall into the M class of the architecture.
Our intention is to provide a readable introduction to the architecture, covering the feature set in
detail and providing practical advice on writing both C and Assembly Language that runs
efficiently on the processor. We assume familiarity with C coding and some knowledge of
microprocessor architectures, although no ARM-specific background is needed. We hope that the
text will be well suited to programmers with a desktop PC or x86 background taking their first steps
into the ARM based world.
The book introduces the fundamentals of the ARM architecture and provides some background on
individual processors (Chapter 2). We then move on to briefly consider some of the tools and
platforms available to those getting started with ARM programming (Chapter 3). Chapters 4, 5 and
6 provide a brisk introduction to ARM Assembly Language programming, covering the various
registers, modes and assembly language instructions. We then switch our focus to the memory
system and look at Caches, Memory Management and Memory Ordering in Chapters 7, 8 and 9.
Dealing with interrupts and other exceptions is described in Chapters 10 to 12 that completes the
coverage of the basic features of ARM processors.
We then move to more software focussed topics and take a look at boot code (Chapter 13) before
going on to look at issues with porting C and assembly code to ARMv7, both from other
architectures and from older versions of the ARM architecture (Chapter 14). Chapter 15covers the
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Application Binary Interface, knowledge of which is useful to both C and Assembly Language
programmers. Profiling and optimizing of code is covered in Chapters 16 and 17. Many of the
techniques presented are not specific to the ARM architecture, but we also provide some
processor-specific hints. We look at floating point and ARM's Advanced SIMD extensions
(NEON) in Chapters 18-20. These chapters are only an introduction to the relevant topics. It
would require a significantly longer piece of text to cover all of the powerful capabilities of
NEON and how to apply these to common signal processing algorithms. Power management is
an important part of ARM programming and is covered in Chapter 21.
Chapters 22-25 cover the area of multi-processing. We take a detailed look at how this is
implemented by ARM and how you can write code to take advantage of it. The main part of the
book is then completed with brief coverage of ARM's security extensions (TrustZone) and the
powerful hardware debug features available to programmers (Chapter 27). Appendices A and B
give a summary of the available ARM, NEON and VFP instructions and Appendix Cgives step
by step instructions for configuring and building ARM Linux.
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References
Cohen, D. On Holy Wars and a Plea for Peace USC/ISI IEN April, 1980,
http://www.ietf.org/rfc/ien/ien137.txt
Furber, Steve, ARM System-on-chip Architecture, 2nd Edition, Addison, Wesley, 2000, ISBN:
9780201675191
Hohl. William ARM Assembly Language: Fundamentals and Techniques CRC Press, 2009.ISBN: 9781439806104
Sloss, Andrew N.; Symes, Dominic; Wright, Chris ARM System Developer's Guide: Designing
and Optimizing System Software Morgan Kaufmann, 2004, ISBN: 9781558608740
Yiu, Joseph The Definitive Guide to the ARM Cortex-M3, 2nd Edition, Newnes, 2009, ISBN:
9780750685344.
ANSI/IEEE Std 754-1985 IEEE Standard for Binary Floating-Point Arithmetic.
ANSI/IEEE Std 754-2008 IEEE Standard for Binary Floating-Point Arithmetic.
ANSI/IEEE Std 1003.1-1990 Standard for Information Technology - Portable Operating
System Interface (POSIX) Base Specifications, Issue 7.
ANSI/IEEE Std 1149.1-2001 IEEE Standard Test Access Port and Boundary-Scan
Architecture.
The ARMArchitecture Reference Manual(Known as the ARM ARM) is a must-read for any
serious ARM programmer. It is available (after registration) from the ARM website. It fully
describes the ARMv7 instruction set architecture, programmers model, system registers, debug
features and memory model. It forms a detailed specification to which all implementations of
ARM processors must adhere.
References to the ARMArchitecture Reference Manualin this document are to:
ARM Architecture Reference Manual - ARMv7-A and ARMv7-R edition (Errata markup)(ARM
DDI 0406)
Note
In the event of a contradiction between this book and the ARM ARM, the ARM ARM is
definitive and must take precedence.
ARM Generic Interrupt Controller Architecture Specification(ARM IHI 0048)
ARM Compiler Toolchain Assembler Reference(DUI 0489)
The individual processor Technical Reference Manuals provide a detailed description of the
processor behavior. They can be obtained from the ARM website documentation area,
http://infocenter.arm.com/help/index.jsp.
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Typographical conventions
This book uses the following typographical conventions:
italic Highlights important notes, introduces special terminology, denotes
internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal
names. Also used for terms in descriptive lists, where appropriate.
monospace Denotes text that you can enter at the keyboard, such as commands, file
and program names, and source code.
monospaceitalic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
< and > Enclose replaceable terms for assembler syntax where they appear in code
or code fragments. For example:
MRC p15, 0, , , ,
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Feedback
ARM welcomes feedback on this product and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
The product name.
The product revision or version.
An explanation with as much information as you can provide. Include symptoms if
appropriate.
Feedback on this book
If you have any comments on this book, send an e-mail to [email protected]. Give:
the title
the number, ARM DEN0013A
the relevant page number(s) to which your comments apply a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.
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Terms and Abbreviations
Terms used in this document are defined here.
AAPCS ARM Architecture Procedure Call Standard.
ABI Application Binary Interface.
ACP Accelerator Coherency Port.
AHB Advanced High-Performance Bus.
AMBA Advanced Microcontroller Bus Architecture.
AMP Asynchronous Multi-Processing.
APB Advanced Peripheral Bus.
ARM ARM The ARM Architecture Reference Manual.
ASIC Application Specific Integrated Circuit.
APSR Application Program Status Register.
ASID Address Space ID.
ATPCS ARM ThumbProcedure Call Standard.
AXI Advanced eXtensible Interface.
BE8 Byte Invariant Big-Endian Mode.
BSP Board Support Package.
BTAC Branch Target Address Cache.
BTB Branch Target Buffer.
CISC Complex Instruction Set Computer.
CP15 Coprocessor 15 - System Control Coprocessor.
CPSR Current Program Status Register.
DAP Debug Access Port.
DBX Direct Bytecode Execution.
DDR Double Data Rate (SDRAM).
DMA Direct Memory Access.
DMB Data Memory Barrier.
DS-5 The ARM development studio.
DSB Data Synchronization Barrier.
DSP Digital Signal Processing.
DSTREAM An ARM debug and trace unit.
DVFS Dynamic Voltage/Frequency Scaling.
EABI Embedded ABI.
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ECC Error Correcting Code.
ECT Embedded Cross Trigger.
ETB Embedded Trace Buffer.
ETM Embedded Trace Macrocell.
FIQ An interrupt type (formerly fast interrupt).
FPSCR Floating Point Status and Control Register.
GCC GNU Compiler Collection.
GIC Generic Interrupt Controller.
GIF Graphics Interchange Format.
GPIO General Purpose Input/Output.
Gprof GNU profiler.
Harvard architecture
Architecture with physically separate storage and signal pathways for
instructions and data.
IDE Integrated development environment.
IRQ Interrupt Request (normally external interrupts).
ISA Instruction Set Architecture.
ISB Instruction Synchronization Barrier.
ISR Interrupt Service Routine.
Jazelle ARMs bytecode acceleration technology.
JIT Just In Time.
L1/L2 Level 1/Level 2.
LSB Least Significant Bit.
MESI A cache coherency protocol with four states, Modified, Exclusive, Shared
and Invalid.
MMU Memory Management Unit.
MPU Memory Protection Unit.
MSB Most Significant Bit.
NEON The ARM SIMD Extensions.
NMI Non-Maskable Interrupt.
Oprofile A Linux system profiler.
QEMU A processor emulator.
PCI Peripheral Component Interconnect. A computer bus standard.
PIPT Physically Indexed, Physically Tagged.
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PLE Preload Engine.
PMU Performance Monitor Unit.
PoC Point of Coherency.
PoU Point of Unification.
PPI Private Peripheral Input.
PSR Program Status Register.
PTE Page Table Entry.
RCT Runtime Compiler Target.
RISC Reduced Instruction Set Computer.
RVCT RealViewCompilation Tools (the ARM Compiler).
SCU Snoop Control Unit.
SGI Software Generated Interrupt.
SIMD Single Instruction, Multiple Data.
SiP System in Package.
SMP Symmetric Multi-Processing.
SoC System on Chip.
SP Stack Pointer.
SPI Shared Peripheral Interrupt.
SPSR Saved Program Status Register.
Streamline A graphical performance analysis tool.
SVC Supervisor Call. (Previously SWI.)
SWI Software Interrupt.
SYS System Mode.
TAP Test Access Port (JTAG Interface).
TCM Tightly Coupled Memory.
TDMI Thumb, Debug, Multiplier, ICE.
TEX Type Extension.
Thumb An instruction set extension to ARM.
Thumb-2 A technology extending the Thumb instruction set to support both 16- and
32-bit instructions.
TLB Translation Lookaside Buffer.
TLS Thread Local Storage.
TrustZone ARMs security extension.
TTB Translation Table Base.
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UAL Unified Assembly Language.
UART Universal Asynchronous Receiver/Transmitter.
UEFI Unified Extensible Firmware Interface.
U-Boot A Linux Bootloader.
USR User mode, a non-privileged processor mode.
VFP ARMs floating point instruction set. Before ARMv7, the VFP extension
was called the Vector Floating-Point Architecture, and was used for vector
operations.
VIC Vectored Interrupt Controller.
VIPT Virtually Indexed, Physically Tagged.
XN Execute Never.
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Chapter 1
Introduction
ARM processors are everywhere. More than 10 billion ARM based devices had been manufactured
by the end of 2008 and at the time of writing (early 2011), it is estimated that around one quarter
of electronic products contain one or more ARM processors. By the end of 2010 over 20 billion
ARM processors had been shipped. It is likely that readers of this book own products containing
ARM-based devices a mobile phone, personal computer, television or car. It might come as a
surprise to programmers more used to the personal computer to learn that the x86 architecture
occupies a much smaller (but still highly lucrative) position in terms of total microprocessor
shipments, with around three billion devices.
The ARM architecture has advanced significantly since the first ARM1 silicon in 1985. The ARM
core is not a single processor, but a whole family of processors, that share common instruction sets
and programmers models and have some degree of backward compatibility.
The purpose of this book is to bring together information from a wide variety of sources to provide
a single guide for programmers who want to develop applications for the latest Cortex-A series of
processors. We will cover hardware concepts such as caches and Memory Management Units, but
only where this is valuable to the application writer. The book is intended to provide information
that will be useful to both assembly language and C programmers. We will look at how complex
operating systems, such as Linux, make use of ARM features and how to take full advantage of the
many advanced capabilities of the ARM processor, in particular writing software for
multi-processing and using the SIMD capabilities of the device
This is not an introductory level book. We assume knowledge of the C programming language and
microprocessors, but not any ARM-specific background. In the allotted space, we cannot hope to
cover every topic in detail. In some chapters, we suggest further reading (referring either to books
or websites) that can give a deeper level of background to the topic in hand, but in this book we will
focus on the ARM-specific detail. We do not assume the use of any particular tool chain. We will
mention both GNU tools and those from ARM during the course of the book.
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Lets begin, however, with a brief look at the history of ARM.
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1.1 History
The first ARM processor was designed within Acorn Computers Ltd by a team led by Sophie
Wilson and Steve Furber, with the first silicon (which worked first time!) produced in April
1985. This ARM1 was quickly replaced by the ARM2 (which added multiplier hardware) which
was used in real systems, including Acorns Archimedes personal computer.
ARM Ltd. was formed in Cambridge, England in November 1990, as Advanced RISC MachinesLtd. It was a joint venture between Apple Computers, Acorn Computers and VLSI Technology
and has outlived two of its parents. The original 12 employees came mainly from the team
within Acorn Computers. One reason for spinning ARM off as a separate company was that the
processor had been selected by Apple Computers for use in its Newton product.
The new company quickly decided that the best way forward for their technology was to license
their intellectual property (IP). Instead of designing, manufacturing and selling the chips
themselves, they would sell rights to their designs to semiconductor companies. These
companies would design the ARM processor into their own products, in a partnership model.
This IP Licensing business is how ARM continues to operate today. ARM was quickly able to
sign up licensees with Sharp, Texas Instruments and Samsung among prominent early
customers. In 1998, ARM Holdings floated on the London Stock Exchange and Nasdaq. At the
time of writing, ARM has nearly 2000 employees and has expanded somewhat from its originalremit of processor design. ARM also licenses Physical IP libraries of cells (NAND gates,
RAM and so forth), graphics and video accelerators and software development products such as
compilers, debuggers, boards and application software.
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1.2 System-on-Chip (SoC)
Chip designers today can produce chips with many millions of transistors. Designing and
verifying such complex circuits has become an extremely difficult task. It is increasingly rare
for all of the parts of such systems to be designed by a single company. In response to this, ARM
Ltd. and other semiconductor IP companies design and verify components (so-called IP blocks
or cores). These are licensed by semiconductor companies who use these blocks in their own
designs and include microprocessors, DSPs, 3D graphics and video controllers, along withmany other functions.
The semiconductor companies take these blocks and integrate many other parts of a particular
system onto the chip, to form a System-on-Chip(SoC). The architects of such devices must
select the appropriate processor(s), memory controllers, on-chip memory, peripherals, bus
interconnect and other logic (perhaps including analog or radio frequency components), in order
to produce a system.
The termApplication Specific Integrated Circuit (ASIC) is one that we will also use in the book.
This is an IC design that is specific to a particular application. An individual ASIC might well
contain an ARM processor, memory and so forth and clearly there is a large overlap with devices
which can be termed SoCs. (The term SoC usually refers to a device with a higher degree of
integration, including many of the parts of the system in a single device, possibly includinganalog, mixed-signal and/or radio frequency circuits.)
The large semiconductor companies investing tens of millions of dollars to create these devices
will typically also make a large investment in software to run on their platform. It would be
uncommon to produce a complex system with a powerful processor without at least having
ported one or more operating systems to it and written device drivers for peripherals.
Of course, powerful operating systems like Linux require significant amounts of memory to run,
more than is usually possible on a single silicon device. The term System-on-Chip is therefore
not always named entirely accurately, as the device does not always contain the whole system.
Apart from the issue of silicon area, it is also often the case that many useful parts of a system
require specialist silicon manufacturing processes that preclude them from being placed on the
same die. An extension of the SoC that addresses this to some extent is the concept ofSystem-in-Package(SiP) that combines a number of individual chips within a single physical
package. Also widely seen is package-on-package stacking. The package used for the SoC chip
contains connections on both the bottom (for connection to a PCB) and top (for connection to a
separate package that might contain a flash memory or a large SDRAM device.
This book is not targeted at any particular SoC device and does not replace the documentation
for the individual product you are targeting for your application. It is important to be aware of
and be able to distinguish between specifications of the processor and behavior (for example,
physical memory maps, peripherals and other features) that is specific to the device you are
using.
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1.3 Embedded systems
An embedded system is conventionally defined as piece of computer hardware that runs
software designed to perform a specific task. Examples of such systems might be TV set-top
boxes, smartcards, routers, disk drives, printers, automobile engine management systems, MP3
players or photocopiers. These contrast with what is generally considered as a computer system,
that is, one that runs a wide range of general purpose software and possesses input and output
devices like a keyboard and a graphical display of some kind.
This distinction is becoming increasingly blurred. Consider the cellular or mobile phone. A
basic model might just perform the task of making phone calls, but a smartphone can run a
complex operating system to which many thousands of applications are available for download.
Embedded systems can contain very simple 8-bit microprocessors, such as an Intel 8051 or PIC
micro-controllers, or some of the more complex 32- or 64-bit processors, such as the ARM
family that form the subject matter for this book. They need some RAM (Random Access
memory) and some form of ROM (Read Only Memory) or other non-volatile storage to hold the
program(s) to be executed by the system. Systems will almost always have additional
peripherals, relating to the actual function of the device typically including UARTs, interrupt
controllers, timers, GPIO (General Purpose I/O) signals, but also potentially quite complex
blocks such asDigital Signal Processing(DSP) orDirect Memory Access(DMA) controllers.
Software running on such systems is typically grouped into two separate parts, the operating
system (OS) and applications that run on top of the OS. A wide range of operating systems are
in use, ranging from simple kernels, to complex Real-Time Operating Systems (RTOS), to
full-featured complex operating systems, of the kind that might be found on a desktop computer.
Microsoft Windows or Linux are familiar examples of the latter. In this book, we will
concentrate mainly on examples from Linux. The source code for Linux is readily available for
inspection by the reader and is likely to be familiar to many programmers. Nevertheless, lessons
learned from Linux are equally applicable to other operating systems.
Applications running in an embedded system take advantage of the services that the OS
provides, but also need to be aware of low level details of the hardware implementation, or
worry about interactions with other applications that are running on the system at the same time.
There are many constraints on embedded systems, that can make programming them rather
more difficult than writing an application for a general purpose processor.
Memory footprint
In many systems, to minimize cost (and power), memory size can be limited. The
programmer could be forced to consider the size of the program and how to
reduce memory usage while it runs.
Real-time behavior
A feature of many systems is that there are deadlines to respond to external
events. This might be a hard requirement (a car braking system mustrespond
within a certain time) or soft requirement (audio processing must completewithin a certain time-frame to avoid a poor user experience - but failure to do so
under rare circumstances may not render the system worthless).
Power In many embedded systems, the power source is a battery and programmers and
hardware designers must take great care to minimize the total energy usage of the
system. For example, by slowing the clock, reducing supply voltage and/or
switching off the processor when there is no work to be done.
Cost: Reducing the bill of materials can be a significant constraint on system design.
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Time to market:
In competitive markets, the time to develop a working product can significantly
impact the success of that product.
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Chapter 2
The ARM Architecture
As described in the opening chapter of this book, ARM does not manufacture silicon devices.
Instead, ARM creates microprocessor designs, which are licensed to semiconductor companies and
OEMs, who integrate them into System-on-Chip devices.
To ensure compatibility between implementations, ARM defines architecture specifications whichdefine how compliant products must behave. Processors implementing the ARM architecture
conform to a particular version of the architecture. There might be multiple processors with
different internal implementations and micro-architectures, different cycle timings and clock
speeds which conform to the same version of the architecture.
The programmer must distinguish between behaviors which are specific to the following:
Architecture This defines behavior common to a set, or family, of processor designs and is
defined in the appropriate ARMArchitecture Reference Manual(ARM
ARM). It covers instruction sets, registers, exception handling and other
programmers model features. The architecture defines behavior that is
visible to the programmer, for example, which registers are available, and
what individual assembly language instructions actually do.
Micro-architecture This defines how the visible behavior specified by the architecture is
implemented. This could include the number of pipeline stages, for example.
It can still have some programmer visible effects, such as how long a
particular instruction takes to execute, or the number of stall cycles after
which the result is available.
Processor A processor is an individual implementation of a micro-architecture. In
theory, there could be multiple processors which implement the same
micro-architecture, but in practice, each processor has unique
micro-architectural characteristics. A processor might be licensed and
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manufactured by many companies. It might therefore, have been
integrated into a wide range of different devices and systems, with a
correspondingly wide range of memory maps, peripherals, and other
implementation specific features Processors are documented in Technical
Reference Manuals, available on the ARM website.
Core We use this term to refer to a separate logical execution unit inside a
multi-core processor.
Individual systems A System-on-Chip (SoC) contains one or more processors and typically
also memory and peripherals. The device could be part of a system which
contains one or more of additional processors, memory, and peripherals.
Documentation is available, not from ARM, but from the supplier of the
individual SoC or board.
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2.1 Architecture versions
Periodically, new versions of the architecture are announced by ARM. These add new features
or make changes to existing behaviors. Such changes are typically backwards compatible,
meaning that user code which ran on older versions of the architecture will continue to run
correctly on new versions. Of course, code written to take advantage of new features will not
run on older processors that lack these features.
In all versions of the architecture, some system features and behaviors are left as
implementation-defined. For example, the architecture does not define cycle timings for
individual instructions or cache sizes. These are determined by the individual
micro-architecture.
Each architecture version might also define one or more optional extensions. These may or may
not be implemented in a particular implementation of a processor. For example, in the ARMv7
architecture, the Advanced SIMD instruction set is available as an optional extension, and we
describe this at length in Chapter 19Introducing NEON.
The ARMv7 architecture also has the concept of Profiles. These are variants of the
architecture describing processors targeting different markets and usages.
The profiles are as follows
A. TheApplicationprofile defines an architecture aimed at high performance
processors, supporting a virtual memory system using a Memory Management
Unit (MMU) and therefore capable of running complex operating systems.
Support for the ARM and Thumb instruction sets is provided.
R. TheReal-timeprofile defines an architecture aimed at systems that need
deterministic timing and low interrupt latency and which do not need support for
a virtual memory system and MMU, but instead use a simpler memory protection
unit (MPU).
M. TheMicrocontrollerprofile defines an architecture aimed at lower
cost/performance systems, where low-latency interrupt processing is vital. It usesa different exception handling model to the other profiles and supports only a
variant of the Thumb instruction set.
Throughout this book, our focus will be on version 7 of the architecture (ARMv7), particularly
ARMv7-A, the Application profile. This is the newest version of the architecture at the time of
writing (2011). It is implemented by the latest high performance processors, such as the
Cortex-A5, Cortex-A8 and Cortex-A9 processors, and also by processors from Marvell and
Qualcomm, among others. We will, where appropriate, point out differences between ARMv7
and older versions of the architecture.
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2.2 Architecture history and extensions
In this section, we look briefly at the development of the architecture through previous versions.
Readers unfamiliar with the ARM architecture should not worry if parts of this description use
terms they dont know, as we will describe all of these topics later in the text.
The ARM architecture changed relatively little between the first test silicon in the mid 1980s
through to the first ARM6 and ARM7 devices of the early 1990s. The first version of thearchitecture was implemented only by the ARM1. Version 2 added multiply and
multiply-accumulate instructions and support for coprocessors, plus some further innovations.
These early processors only supported 26-bits of address space.Version 3 of the architecture
separated the program counter and program status registers and added several new modes,
enabling support for 32-bits of address space. Version 4 adds support for halfword load and store
operations and an additional kernel-level privilege mode.
The ARMv4T architecture, which introduced the Thumb (16-bit) instruction set, was
implemented by the ARM7TDMI and ARM9TDMI processors, products which have shipped
in their billions. The ARMv5TE architecture added improvements for DSP-type operations and
saturated arithmetic and to ARM/Thumb interworking. ARMv6 made a number of
enhancements, including support for unaligned memory access, significant changes to the
memory architecture and for multi-processor support, plus some support for SIMD operationsoperating on bytes/halfwords within the 32-bit general purpose registers. It also provided a
number of optional extensions, notably Thumb-2 and Security Extensions (TrustZone).
Thumb-2 extends Thumb to be a variable length (16-bit and 32-bit) instruction set. The
ARMv7-A architecture makes the Thumb2 extensions mandatory and adds the Advanced SIMD
extensions (NEON), described in Chapter 19and Chapter 20.
A brief note on the naming of processors might be useful for readers. For a number of years,
ARM adopted a sequential numbering system for processors with ARM9 following ARM8,
which came after ARM7. Various numbers and letters were appended to the base family to
denote different variants. For example, the ARM7TDMI processor has T for Thumb, D for
Debug, M for a fast multiplier and I for embedded Ice. For the ARMv7 architecture, ARM
Limited adopted the brand name Cortexfor many of its processors, with a supplementary letter
indicating which of the three profiles (A, R or M) the processor supports. Figure 2-1 on page 2-5shows how different versions of the architecture correspond to different processor
implementations. The figure is not comprehensive and does not include all architecture versions
or processor implementations.
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Figure 2-1 Architecture and processors
In Figure 2-2, we show the development of the architecture over time, illustrating additions to
the architecture at each new version. Almost all architecture changes are backward-compatible,
meaning unprivileged software written for the ARMv4T architecture can still be used on
ARMv7 processors.
Figure 2-2 Architecture history
Architecture
v4 / v4T
Architecture
v5
Architecture
v6
Architecture
v7
ARM7TDMI
ARM920TStrongARM
ARM926EJ-S
ARM946E-SXScale
ARM1136J-S
ARM1176JZ-SARM1156T2-S
ARMv7-A
Cortex-A5
Cortex-A8
Cortex-A9
ARMv7-R
Cortex-R4
ARMv7-M
Cortex-M3
ARMv6-M
Cortex-M0 ARMv7E-M
Cortex-M4
4T 5 6 7
Halfword and signed
halfword/byte support
System mode
Thumb instruction
set
Improved ARM/Thumb
Interworking
CLZ
Saturated arithmetic
DSP multiply-accumulate
Instructions
Extensions:
Jazelle (v5TEJ)
SIMD instructions
Multi-processing
v6 memory architecture
Unaligned data support
Extensions:
Thumb-2 (v6T2) TrustZone (v6Z)
Multiprocessor (v6K)
Thumb only (v6-M)
Thumb technology
NEON
TrustZone
Profiles:
v7-A (Applications)
NEON
v7-R (Real-time)
Hardware divide
NEON
v7-M (Microcontroller)
Hardware divide
Thumb only
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Individual chapters of this book will cover these architecture topics in greater detail, but here
we will briefly introduce a number of architecture elements.
2.2.1 DSP multiply-accumulate and saturated arithmetic instructions
These instructions, added in the ARMv5TE architecture, improve the capability for digital
signal processing and multimedia software and are denoted by the letter E. The new instructions
provide many variations of signed multiply-accumulate, saturated add and subtract, and countleading zeros and are present in all later versions of the architecture. In many cases, this made
it possible to remove a simple separate DSP from the system.
2.2.2 Jazelle
Jazelle-DBX (Direct Bytecode eXecution) enables a subset of Java bytecodes to be executed
directly within hardware as a third execution state (and instruction set). Support for this is
denoted by the J in the ARMv5TEJ architecture. Support for this state is mandatory from
ARMv6, although a specific ARM core can optionally implement actual Jazelle hardware
acceleration, or handle the bytecodes through software emulation. The Cortex-A9 and
Cortex-A5 processors offer configurable support for Jazelle.
Jazelle-DBX is best suited to providing high performance Java in very memory limited systems
(for example, feature phone or low-cost embedded use). In todays systems, it is mainly used for
backwards compatibility.
2.2.3 Thumb Execution Environment (ThumbEE)
This is also described as Jazelle-RCT (Runtime Compilation Target). It involves small changes
to the Thumb instruction set that make it a better target for code generated at runtime in
controlled environments (for example, by managed languages like Java, Dalvik, C#, Python or
Perl). The feature set includes automatic null pointer checks on loads and stores and instructions
to check array bounds, plus special instructions to call a handler. These are small sections of
critical code, used to implement a specific feature of a high level language. These changes come
from re-purposing a handful of opcodes.
ThumbEE is designed to be used by high-performance just-in-time or ahead-of-time compilers,
where it can reduce the code size of recompiled code. Compilation of managed code is outside
the scope of this document.
2.2.4 Thumb-2
Thumb-2 technology was added in ARMv6T2. This technology extended the original 16-bit
Thumb instruction set to support 32-bit instructions. The combined 16-bit and 32-bit Thumb
instruction set achieves similar code density to the original Thumb instruction set, but with
performance similar to the 32-bit ARM instruction set. The resulting Thumb instruction set
provides virtually all the features of the ARM instruction set, plus some additional capabilities.
2.2.5 Security extensions (TrustZone)
The TrustZone extensions were added in ARMv6Z and are present in the ARMv7-A profile
covered in this book. TrustZone provides two virtual processors with rigorously enforced
hardware access control between the two. This means that the processor provides two worlds,
Secure and Normal, with each world operating independently of the other in a way which
prevents information leakage from the secure world to the non-secure and which stops
non-trusted code running in the secure world. This is described in more detail, in Chapter 26
Security.
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2.2.6 VFP
Before ARMv7, the VFP extension was called the Vector Floating-Point Architecture, and was
used for vector operations.VFP is an extension which implements single-precision and
optionally, double-precision floating-point arithmetic, compliant with the ANSI/IEEE Standard
for Floating Point Arithmetic.
2.2.7 Advanced SIMD (NEON)
ARMs NEON technology provides an implementation of the Advanced SIMD instruction set,
with separate register files (shared with VFP). Some implementations have a separate NEON
pipeline back-end. It supports 8-, 16-, 32- and 64-bit integer and single-precision (32-bit)
floating-point data, which can be operated on as vectors in 64-bit and 128-bit registers.
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2.3 Key points of the ARM Cortex-A series architecture
Here we summarize a number of key points common to all of the Cortex-A family of devices.
32-bit RISC processor, with 16 32-bit visible registers with mode-based register
banking.
Modified Harvard Architecture (separate, concurrent access to instructions and data).
Load/Store Architecture.
Thumb-2 technology as standard.
VFP and NEON options which are expected to become standard in general purpose
applications processor space.
Backward compatibility with code from previous ARM cores.
Full 4GB virtual and physical address spaces, with no restrictions imposed by the
architecture.
Efficient hardware page table walking for virtual to physical address translation.
Virtual Memory for page sizes of 4KB, 64KB, 1MB and 16MB. Cacheability and access
permissions can be set on a per-page basis.
Big-endian and little-endian support.
Unaligned access support for load/store instructions with 8-bit/ 16-bit/ 32-bit integer data
sizes.
SMP support on MPCorevariants, with full data coherency from the L1 cache level.
Automatic cache and TLB maintenance propagation provides high efficiency SMP
operation.
Physically indexed, physically tagged(PIPT) data caches.
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2.4 Processors and pipelines
In this chapter, we briefly look at some ARM processors and identify which processor
implements which architecture version. We then take a slightly more detailed look at some of
the individual processors which implement architecture version v7-A, which forms the main
focus of this book. Some terminology will be used in this chapter which may be unfamiliar to
the first-time user of ARM processors and which will not be explained until later in the book.
Table 2-1indicates the architecture version implemented by a number of older ARM cores.
Table 2-2shows the Cortex family of processors.
In the next section, well take a closer look at each of the processors which implement the
ARMv7-A architecture.
2.4.1 The Cortex-A5 processor
The Cortex-A5 processor supports all ARMv7-A architectural features, including the TrustZone
security extensions and the NEON multimedia processing engine. It is extremely area and
power efficient, but has lower maximum performance than the Cortex-A8 or Cortex-A9
processors. Both single and multi-core versions of the Cortex-A5 processor are available.
The Cortex-A5 processor integer core has a single-issue, 8-stage pipeline. It can dual issue
branches in some circumstances and contains sophisticated branch prediction logic to reduce
penalties associated with pipeline refills. Both NEON and floating-point hardware support are
optional. The Cortex-A5 processor VFP implements VFPv4, which adds both the half-precision
extensions and the Fused Multiply Add instructions to the features of VFPv3. (Support for
Table 2-1 Older ARM processors and architectures
Architecture Version Applications Processor Embedded Processor
v4T ARM720T
ARM920T
ARM922T
ARM7TDMI
v5TE ARM946E-S
ARM966E-S
ARM968E-S
v5TEJ ARM926EJ-S
v6K ARM1136J(F)-S
ARM11 MPCore
v6T2 ARM1156T2-S
v6K + Security extensions ARM1176JZ(F)-S
Table 2-2 Cortex Processors and Architecture Versions
v7-A (Applications) v7-R (Real Time) v6-M/v7-M (Microcontroller)
Cortex-A5 (Single/MP) Cortex-R4 Cortex-M0 (ARMv6-M)
Cortex-A8 Cortex-M1 (ARMv6-M)
Cortex-A9 (Single/MP) Cortex-M3 (ARMv7-M)
Cortex-M4(F) (ARMv7E-M)
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half-precision was optional in VFPv3). It supports the ARM and Thumb instruction sets plus the
Jazelle-DBX and Jazelle-RCT technology. The size of the level 1 instruction and data caches is
configurable (by the hardware implementer) from 4KB to 64KB.
2.4.2 The Cortex-A8 processor
The Cortex-A8 processor was the first to implement the ARMv7-A architecture. It is available
in a number of difference devices, including the S5PC100 from Samsung, the OMAP3530 fromTexas Instruments and the i.MX515 from Freescale. A wide range of device performances are
available, with some giving clock speeds of more than 1GHz.
The Cortex-A8 processor has a considerably more complex micro-architecture compared with
previous ARM processors. Its integer core has dual symmetric, 13 stage instruction pipelines,
with in-order issue of instructions. The NEON pipeline has an additional 10 pipeline stages,
supporting both integer and floating point 64/128-bit SIMD. VFPv3 floating point is supported,
as is Jazelle-RCT.
Figure 2-3is a block diagram showing the internal structure of the Cortex-A8 processor,
including the pipelines.
Figure 2-3 The Cortex-A8 processor integer and NEON pipelines
The separate instruction and data level 1 caches are 16KB or 32KB in size. They are
supplemented by an integrated, unified level 2 cache, which can be up to 1MB in size, with a
16-word line length. The level 1 data cache and level 2 cache both have a 128-bit wide data
Embedded Trace Macrocell
ALU and Load/Store Execute NEON
Integer ALU
Integer MUL
Integer shift
FP ADD
FP MUL
IEEE FP
LS permuteLoad/Store
data queue
ALU pipe 0
MUL pipe 0
ALU pipe 1
LS pipe 0/1
Instruction
Decode
Instruction
Fetch
BIU pipeline
L3 memory system
L1 L2 L3 L4 L5 L6 L7 L8 L9T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
M0 M1 M2 M3 N1 N2 N3 N4 N5 N6F0 F1 F2 D0 D1 D2 D3 D4 E0 E1 E2 E3 E4 E5
NEO
N
RegisterFile
NEON
InstructionDecode
Branch mispredict
penalty
Replay
penalty
Integer register writeback
NEON store data
External
trace port
L1instruction
cache miss
L1 data
cache miss
L2 data L1 data
Archi
tecturalRegisterFile
L2 tag L2 data
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interface to the core. The level 1 data cache is virtually indexed, but physically tagged, while
level 2 uses physical addresses for both index and tags. Data used by NEON is, by default, not
allocated to L1 (although NEON can read and write data that is already in the L1 data cache).
2.4.3 The Cortex-A9 processor
The Cortex-A9MPCore processor and the Cortex-A9 uniprocessor provide higher performance
than the Cortex-A5 or Cortex-A8 processors, with clock speeds in excess of 1GHz andperformance of 2.5DMIPS/MHz. The ARM, Thumb, Thumb-2, TrustZone, Jazelle-RCT and
DBX technologies are all supported.
The level 1 cache system provides hardware support for cache coherency for between one and
four cores for multi-core software. A level 2 cache is optionally connected outside of the
processor. ARM supplies a level 2 cache controller (PL310/L2C-310) which supports caches of
up to 8MB in size. The processor also contains an integrated interrupt controller, an
implementation of ARMs Generic Interrupt Controller(GIC) architecture specification. This
can be configured to provide support for up to 224 interrupt sources.
Figure 2-4 Block Diagram of Cortex-A9 Single Core
Devices containing the Cortex-A9 processor include nVidias dual-core Tegra-2, the
SPEAr1300 from ST and TIs OMAP4 platform.
CoreSight
Debug Access Port
Profiling
Monitor Block
Dual-instruction
Decode Stage
Fast Loop Mode
Instruction
Cache
Branch
Prediction
Virtual to
Physical
Register
pool
Register
Rename stage
Branches
Out-of-Order
multi-issue with
speculation
Instruction queue
And
Dispatch
3+1 Dispatch Stage
Auto-prefetcher
Load-Store Unit
Data Cache
Memory System
uTLB
MMU
Program
Trace
Unit
Out-of-orderWritebackStage
ALU/MUL
ALU
FPU/NEON
AddressInstruction
queue
Pre
dicti
on
queue
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2.4.4 The Cortex-A15 processor
The Cortex-A15 MPCore processor was announced by ARM in September 2010. It has an
out-of-order superscalar pipeline and a number of improvements to floating point and NEON
media performance. It is application compatible with the other processors described in this
book. The Cortex-A15 MPCore processor introduces some new capabilities, including support
for full hardware virtualization and Large Physical Address Extensions (LPAE), which enables
addressing of up to 1TB of memory. As the Cortex-A15 MPCore processor will not beencountered by most readers for some time, it is not mentioned further in this book.
2.4.5 Qualcomm Scorpion
ARM is not the only company which designs processors compliant with the ARMv7-A
Instruction Set Architecture. In 2005, Qualcomm Inc. announced that it was creating its own
implementation under license from ARM, with the name Scorpion. The Scorpion processor is
available as part of Qualcomms Snapdragon platform, which contains the features necessary to
implement netbooks, smartphones or other mobile internet devices.
Relatively little information has been made publicly available by Qualcomm, although it has
been commented that Scorpion has a number of similarities with the Cortex-A8 processor. It is
an implementation of ARMv7-A, is superscalar and dual issue and has support for both VFPand NEON (called the VeNum media processing engine in Qualcomm press releases). There are
a number of differences, however. Scorpion can process 128 bits of data in parallel in its NEON
implementation. Scorpion has a 13-stage load/store pipeline and two integer pipelines. One of
these is 10 stages long and can execute only simple arithmetic instructions (for example adds or
subtracts), while the other is 12 stages and can execute all data processing operations, including
multiplies. Scorpion also has a 23-stage floating-point/SIMD pipeline, and VFPv3 operations
are pipelined.
We will not specifically mention Scorpion again in this text. However, as the processor
conforms to the ARMv7-A architecture specification, most of the information presented here
will apply also to Scorpion.
2.4.6 Marvell Sheeva
Marvell is another company which designs and sells processors based on the ARM Architecture.
At the time of writing, Marvell has four families of ARM processors, the Armada 100, Armada
500, Armada 600, and Armada 1000. Marvell has designed a number of ARM processor
implementations, ranging from the Sheeva PJ1 (ARMv5 compatible) to Sheeva PJ4 (ARMv7
compatible). The latter is used in the Armada 500 and Armada 600 family devices.
The Marvell devices do not support the NEON SIMD instruction set, but instead use the
Wireless MMX2 technology, acquired from Intel. The Armada 510 contains 32KB I and D
caches plus an integrated 512KB level 2 cache and support for VFPv3. The Armada 610 is built
on a low power silicon process and has a smaller (256KB) level 2 cache and can be clocked
at the slightly slower rate than Armada 510. We will not specifically mention these processorsagain in this text
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Chapter 3
Tools, Operating Systems and Boards
ARM processors can be found in a very wide range of devices, running a correspondingly wide
range of software. Many readers will have ready access to appropriate hardware, tools and
operating systems, but before we proceed to look at the underlying architecture, it might be useful
to some readers to present an overview of some of these readily available compilation tools,
ARM-based hardware and Linux operating system distributions.
In this chapter, we will provide a brief mention of a number of interesting commercially available
development boards. We will provide some information about the Linux Operating System and
some useful associated tools. However, information about open source software and off-the-shelf
boards is likely to change rapidly.
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3.1 Linux distributions
Linux is a Unix-like operating system kernel, originally developed by Linus Torvalds, who
continues to maintain the official kernel. It is open source, distributed under the GNU Public
License, widely-used and available on a large number of different processor architectures.
A number of free Linux distributions exist for ARM processors, including Debian and Ubuntu,
Fedora and Gentoo.You can obtain pre-built Linux images at http://ww.arm.com/linuxor read the ARM Linux Wiki
athttp://ww.arm.com/linux.
In Appendix C, we will look at how to build an ARM Linux system. Before doing that, we will
briefly look at the basics of ARM Linux.
3.1.1 ARM Linux
ARM Linux is the name given to the port of the Linux kernel to ARM processors. This kernel
is actively developed, with significant input from ARM to provide kernel support for new
processors and architecture versions. The ARM Embedded Linux distribution includes the
kernel, filesystem and U-Boot bootloader.
It might seem strange to some readers that a book about the Cortex-A series of processors
contains information about Linux. There are several reasons for this. Linux source code is
available to all readers and represents a huge learning resource. In addition, it is easy to program
and there are many useful resources with existing code and explanations. Many readers will be
familiar with Linux, as it can be run on most processor architectures. By explaining how Linux
features like virtual memory, multi-tasking, shared libraries and so forth are implemented in
ARM Linux, readers will be able to apply their understanding to other operating systems
commonly used on ARM processors. The scalability of Linux is another factor it can run on
the most powerful ARM processors, and its derivative uCLinux is also commonly used on much
smaller processors, including the Cortex-M3 or ARM7TDMI processors. It can run on both the
ARM and Thumb ISAs, in little- or big-endian and with or without a memory management unit.
Linux makes large amounts of system and kernel information available to user applications by
using virtual filesystems. These virtual files mean that we dont have to know how to program
the kernel to access many hardware features. An example is /proc/cpuinfo. Reading this file on
a Cortex-A8 processor might give an output like that in Example 3-1. This lets code determine
useful information about the system it is running on, without having to directly interact with the
hardware.
Example 3-1 Output of /proc/cpuinfo on the Cortex-A8 processor
Processor : ARMv7 Processor rev 7 (v7l)
BogoMIPS : 499.92
Features : swp half thumb fastmult vfp edsp neon vfpv3CPU implementer : 0x41CPU architecture: 7CPU variant : 0x1
CPU part : 0xc08CPU revision : 7
In this book, we can merely scratch the surface of what there is to be said about Linux
development. What we hope to do here is to show some ways in which programming for an
embedded ARM based system differs from a desktop x86 environment and to give some
pointers to useful tools, which the reader might care to investigate further.
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3.1.2 Linaro
Linaro is a non-profit organization which works on a range of open source software running on
ARM processors, including kernel related tools and software and middleware. It is a
collaborative effort between a number of technology companies to provide engineering help and
resources to the open source community. Linaro does not produce a Linux distribution, nor is it
tied to any particular distribution or board. Instead, Linaro works to produce software and tools
which interact directly with the ARM processor, to provide a common software platform for useby board support package developers. Its focus is on tools to help you write and debug code, on
low-level software which interacts with the underlying hardware and on key pieces of
middleware. Linaro engineers work on the kernel and tools, graphics and multimedia and power
management. Linaro provides patches to upstream projects and makes monthly source tree
tarballs available, with an integrated build every six months to consolidate the work.
See http://www.linaro.org/for more information about Linaro.
3.1.3 Linux terminology
Here, we define some terms which we will use when describing how the Linux kernel interacts
with the underlying ARM Architecture:
Thread A thread is a piece of code running in the system. A thread group, or process, is
a collection of threads which share a memory map, typically working together as
part of an application. In an SMP system, threads can be spread across multiple
processors, even if they are part of the same process.
Processes These are created using the fork()system call. Creation of new threads is
performed with the clone()system call. Each thread has its own stack and
associated kernel structures, although threads belonging to the same process can
share some kernel structures, including file handles and MMU page tables.
Scheduler This is a vital part of the kernel which has a list of all the current threads. It knows
which threads are ready to be run and which are currently not able to run. It
dynamically calculates priority levels for each thread and schedules the highestpriority thread to be run next. It is called after an interrupt has been handled. The
scheduler is also explicitly called by the kernel via the schedule()function, for
example, when an application executing a system call needs to sleep. The system
will have a timer based interrupt which results in the scheduler being called at
regular intervals. This enables the OS to implement time-division multiplexing,
where many threads share the processor, each running for a certain amount of
time, giving the user the illusion that many applications are running
simultaneously.
System Calls Linux applications run in user (unprivileged) mode. Many parts of the system are
not directly accessible in user mode. For example, the kernel might prevent user
mode programs from accessing peripherals, kernel memory space and the
memory space of other user mode programs. Access to some features of thesystem control coprocessor (CP15) is not permitted in user mode. The kernel
provides an interface (via the SVCinstruction) which permits an application to call
kernel services. Execution is transferred to the kernel through the SVCexception
handler, which returns to the user application when the system call is complete.
Libraries Linux applications are, with very few exceptions, not loaded as complete
pre-built binaries. Instead, the application relies on external support code linked
from files called shared libraries. This has the advantage of saving memory space,
in that the library only needs to be loaded into RAM once and is more likely to be
in the cache as it can be used by other applications. Also, updates to the library
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do not require every application to be rebuilt. However, this dynamic loading
means that the library code must not rely on being in a particular location in
memory.
Files These are essentially blocks of data which are referred to using a pathname
attached to them. Devices nodes have pathnames like files, but instead of being
linked to blocks of data, they are linked to device drivers which handle real I/O
devices like an LCD display, disk drive or mouse. When an application opens,read or writes a device, control is passed to specific routines in the kernel that
handle that device.
3.1.4 Embedded Linux
Linux-based systems are used all the way from servers via the desktop, through mobile devices
and al