Download - Combinational verilog
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Outline Conditional operator
If-else statement
Case statement
Casex, casez
Examples
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Combinational circuits0
1
w0
En
y0w1 y1
y2y3
inputs
outputs
1) Outputs only depend on inputs2) Could include: gates, multiplexers, encoders, decoders,
code converters, comparators 3) Verilog description: gates, logic expression, behavior
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Multiplexer examplesmodule mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;
assign f = s ? w1 : w0;
endmodule
module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;
reg f;
always @(w0 or w1 or s)
f = s ? w1 : w0;
endmodule
Conditional operatorin continuous assignment
Conditional operator
in procedural statement
1) f is reg2) Include all input signals
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Nesting conditional operatorsmodule mux4to1 (w0, w1, w2, w3, S, f);
input w0, w1, w2, w3;
input [1:0] S;
output f;
assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);
endmodule
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if-else Format
if(conditional_expression) statement;
else statement; Behavior
If the conditional_expression is true, then the firststatement is executed;
Or else the second statement is executed. Used inside an always block, the statements are
procedural.
beginend
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if-else examplesmodule mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;
reg f;
always @(w0 or w1 or s)
if(s= =0)
f = w0;else
f = w1;
endmodule
reg data type
Include all input signals
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If else ifelse ifmodule mux4to1 (w0, w1, w2, w3, S, f);
input w0, w1, w2, w3;
input [1:0] S;
output f;
reg f;
always @(w0 or w1 or w2 or w3 or S)
if(S = = 2'b00)
f = w0;
elseif(S = = 2'b01)
f = w1;elseif(S = = 2'b10)
f = w2;
elseif(S = = 2'b11)
f = w3;
endmodule
module mux4to1 (W, S, f);
input [0:3] W;
input [1:0] S;
output f;
reg f;
always @(W or S)
if(S = = 0)
f = W[0];
else if(S = = 1)
f = W[1];else if(S = = 2)
f = W[2];
else if(S = = 3)
f = W[3];
endmodule
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Hierarchical 16-to-1 Multiplexer
module mux16to1 (W, S16, f);
input [0:15] W;
input [3:0] S16;
output f;wire [0:3] M;
mux4to1 Mux1 (W[0:3], S16[1:0], M[0]);
mux4to1 Mux2 (W[4:7], S16[1:0], M[1]);
mux4to1 Mux3 (W[8:11], S16[1:0], M[2]);mux4to1 Mux4 (W[12:15], S16[1:0], M[3]);
mux4to1 Mux5 (M[0:3], S16[3:2], f);
endmodule
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Case statement Formatcase(expression)
alternative1: statement;
alternative2: statement;
alternativej: statement;
[default: statement;]
endcase
1) Many possible alternatives2) Expression and each alternative are
compared bit by bit.
3) If there is a match, the statement isexecuted4) If the alternatives do not cover all
possibilities, default should be included.Otherwise, a sequential circuit will begenerated
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Multiplexer using casemodule mux4to1 (W, S, f);input [0:3] W;
input [1:0] S;
output f;
reg f;
always @(W or S)
case (S)
0: f = W[0];
1: f = W[1];2: f = W[2];
3: f = W[3];
endcase
endmodule
or binary numbers
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Decoder using casemodule dec2to4 (W, Y, En);
input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;
always @(W or En)
case ({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
Concatenate operatorDefault for En=0
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Decoder using if-else, casemodule dec2to4 (W, Y, En);
input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;
always @(W or En)begin
if(En == 0)
Y = 4'b0000;
else
case (W)
0: Y = 4'b1000;
1: Y = 4'b0100;
2: Y = 4'b0010;
3: Y = 4'b0001;
endcase
end
endmodule
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Hierarchical code for 4-16 decoder
module dec4to16 (W, Y, En);
input [3:0] W;
input En;
output [0:15] Y;
wire [0:3] M;
dec2to4 Dec1 (W[3:2], M[0:3], En);
dec2to4 Dec2 (W[1:0], Y[0:3], M[0]);
dec2to4 Dec3 (W[1:0], Y[4:7], M[1]);
dec2to4 Dec4 (W[1:0], Y[8:11], M[2]);dec2to4 Dec5 (W[1:0], Y[12:15], M[3]);
endmodule
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BCD-to-7-segment decoder
module seg7 (bcd, leds);input [3:0] bcd;
output [1:7] leds;
reg [1:7] leds;
always @(bcd)
case (bcd) //abcdefg
0: leds = 7'b1111110;
1: leds = 7'b0110000;
2: leds = 7'b1101101;
3: leds = 7'b1111001;
4: leds = 7'b0110011;
5: leds = 7'b1011011;
6: leds = 7'b1011111;
7: leds = 7'b1110000;
8: leds = 7'b1111111;
9: leds = 7'b1111011;
default: leds = 7'bx;
endcase
endmodule
comment
Xdont-care
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ALU Example
// ALU Example
module alu(s, A, B, F);
input [2:0] s;input [3:0] A, B;
output [3:0] F;
reg [3:0] F;
always @(s or A or B)
case (s)0: F = 4'b0000;
1: F = B - A;
2: F = A - B;
3: F = A + B;
4: F = A ^ B;
5: F = A | B;6: F = A & B;
7: F = 4'b1111;
endcase
endmodule
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casex and casez case : bit-by-bit comparison {0,1,z,x}
case (s)
s1: // 001 001; 0x10x1; zx0zx0
casez: treat all z as dont care
// 001 001; 0x10x1; 1x0zx0
casex: treat all z and x as dont care
// 001 001; 1001xx; 010z1x
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Priority encoder
module priority (W, Y, z);
input [3:0] W;
output [1:0] Y;
output z;
reg [1:0] Y;
reg z;
always @(W)
begin
z = 1;
casex(W)
4'b1xxx: Y = 3;
4'b01xx: Y = 2;
4'b001x: Y = 1;
4'b0001: Y = 0;
default: begin
z = 0;Y = 2'bx;
end
endcase
end
endmodule
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FA ExampleA
BS
Cout
halfadder.hdlWe assigned regs tothese
and wires to these
x
ys
cout
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Full Adder (one implementation)
A
B
CS
cout
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Combining ModulesA
B
S
Cout
A
B
S
Cout
A
B
C
sum
cout
this is a wire.Lets call it
con1
another wire.Lets call it
con2
third wire.Lets call it
con3
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halfadder.vmodule halfadder (a, b, s, cout);input a, b;output s, cout;
xor (s, a, b);and (cout, a, b);
endmodule
This defines the inputs andoutputs to/from a module
Defines which are inputs andwhich are outputs
This is the type of gate (and, or,not, xor are the ones well use
These are the inputs and outputsto/from the gate. Output is
always first, followed by inputs.
This is the circuit name
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Two half adders one fullmodule fulladder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;wire con1,con2,con3;
halfadder ha1(a,b,con1,con2);
halfadder ha2(cin,con1,sum,con3);
or (cout,con2,con3);
endmodule
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Test Benchmodule main;
reg a, b, c;wire sum, carry;
fulladder add(a,b,c,sum,carry);initialbegin
a = 0; b = 0; c = 0;#5a = 0; b = 1; c = 0;#5a = 1; b = 0; c = 1;#5
a = 1; b = 1; c = 1;#5
endendmodule
module testfull;
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Testing?
module testfull;
reg a, b, c;wire s, cout;
fulladder myfulladder (a, b, c, s, cout);
initialbegin
a = 1'b0; b = 1'b0; c = 1'b0;#10 $display ($time, " cout: %b s: %b", cout, s);#10 a = 1'b0; b = 1'b0; c = 1'b1;#10 $display ($time, " cout: %b s: %b", cout, s);#10 a = 1'b0; b = 1'b1; c = 1'b0;#10 $display ($time, " cout: %b s: %b", cout, s);#10 a = 1'b0; b = 1'b1; c = 1'b1;#10 $display ($time, " cout: %b s: %b", cout, s);#10 a = 1'b1; b = 1'b0; c = 1'b0;#10 $display ($time, " cout: %b s: %b", cout, s);#10 a = 1'b1; b = 1'b0; c = 1'b1;#10 $display ($time, " cout: %b s: %b", cout, s);#10 a = 1'b1; b = 1'b1; c = 1'b0;
#10 $display ($time, " cout: %b s: %b", cout, s);#10 a = 1'b1; b = 1'b1; c = 1'b1;#10 $display ($time, " cout: %b s: %b", cout, s);#10 $finish;
end
endmodule