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VHDL 0INTRODUCTION TO
VHDLK H Wongkhwong@cse2609-8397,Room 907 SHB-Engineering buildinghttp://www.cse.cuhk.edu.hk/~khwong/www2/ceng3430/ceng3430.html
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CENG3430 Rapid Prototyping of Digital Systems
You will learn: The hardware description language VHDL Techniques to build a Central Processing Unit (CPU) High speed logic circuits analysis: time delay estimation, testing,
power supply stability, etc.
1 entity and2 is port ( a,b : in std_logic;2 c : out std_logic);3 end and2 4 architecture and2_arch of and2 5 begin6 c
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A QUICK RUN
THROUGHOverview
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Overview
What is VHDL used for? To design
Hardware systems (an industrial standard) Microprocessors: Arm7 etc Design new Digital systems: e.g. mobile phone, camera chips
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Motivations Learn to design digital systems. Provide knowledge for you to :
Design products: Mp3, mp4 players, portable games, mobile phones.
Advanced examples Image processing Computer vision Super computer
Start a business.
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Examples of digital system design Mass products
Mp3, mp4, video players PDA, mobile phones
Novel products Wearable computer Robots
Research Real time edge detection for
computer vision
VHDL 0 (v.3A) : Introduction 6
www.wearable-consult.com/images/buergy_hwd.jpg
www.cnn.com/...
/06/10/mars.rover/index.html
http://youtu.be/LvzBkylNZ5chttp://youtu.be/LvzBkylNZ5chttp://www.cnn.com/.../06/10/mars.rover/index.htmlhttp://www.cnn.com/.../06/10/mars.rover/index.htmlhttp://youtu.be/LvzBkylNZ5chttp://www.cnn.com/.../06/10/mars.rover/index.htmlhttp://youtu.be/LvzBkylNZ5chttp://youtu.be/LvzBkylNZ5c -
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To learn
Design digital processing components usingprogrammable logic Two existing Methods
(a) Schematic, (too complicated But is suitable to describe the top level design like a data flow block diagram
(b) Language (e.g. VHDL-- V ery-High-Speed-Integrated-Circuits Hardware Description Language): Each module in the schematiccan be written in VHDL.
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DIGITAL DESIGNWork Flow
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Digital Design Work Flow Idea generation Drafting on paper Design the chip (use VHDL)
Test Manufacturing production line design Quality control
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WE USE IN OUR LABHardware: FPGA (Field Programmable Gate Array)
T he hardware can be reprogrammable , so you can change your designrapidly and easily with no additional hardware manufacturing cost.
Software: VHDL (V ery-High-Speed-Integrated-Circuits Hardware Description Language)
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Re-programmable Hardware: FPGA FieldProgrammable Gate Array
So what is inside an FPGA
IOB=Input/Output block CLB=Configurable Logicblock (static ram based)
Change the CLBs to getthe desired functions
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From http://www.alldatasheet.co.kr/datasheet-
pdf/pdf_kor/49173/XILINX/XCS10-3PC84C.html
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Inside a CLB (Configurable Logic block ) The CLB is a fixed design but you can change the logicfunction for generating output from input G1-G4 by
reprogramming the bits in the logic function lookup table. This will change the overall logic function of the CLB
Re-programming the logic table
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http://www.design-reuse.com/news_img/20100913_1.gif http://pldworld.biz/html/technote/pldesignline/bobz-02.gif
CLB
FPGA CLB(Configurable Logic block )
http://www.design-reuse.com/news_img/20100913_1.gifhttp://www.design-reuse.com/news_img/20100913_1.gifhttp://www.design-reuse.com/news_img/20100913_1.gifhttp://www.design-reuse.com/news_img/20100913_1.gif -
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Software: to program an FPGA
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1 entity and2 is port ( a,b : in std_logic;2 c : out std_logic);3 end and2
4 architecture and2_arch of and2 5 begin6 c
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1 entity and2 is port ( a,b : in std_logic;2 c : out std_logic);3 end and2 4 architecture and2_arch of and2 5 begin6 c
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Timing simulation
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Summary of VHDL For hardware Design Parallel language (not sequential) Different! (not the same as C++ or Java)
VHDL is the industrial standard for CE.
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An example: And gate in VHDL
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COMPUTERENGINEERING MARKET
and VHDL
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Major high-tech companies , a comparison in 2011 (from wiki) Wiki: 20092,589.6 , 1 6,000 http://money.163.com 500 ,
(2011-08-25)
Company Apple IBM Microsoft Intel HP TSMC
(largestasset in
Taiwanstockmarket)
Huawei
(Telecomequipmt,China
largeprivatecompany)
RevenueUS Billion
65.23 99 69.94 43.6 99.87 13.98 21.8
Asset 75.1 113.5 108.7 63.2 124.5 20.43 Notknown
ProfitUS Billion
14.01 14 23.15 11.46 14.83 5.55 2.67
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http://zh.wikipedia.org/wiki/2009%E5%B9%B4http://zh.wikipedia.org/wiki/2009%E5%B9%B4http://zh.wikipedia.org/wiki/2009%E5%B9%B4http://zh.wikipedia.org/wiki/2009%E5%B9%B4 -
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Major companies , a comparison in 2011(from wiki)
Company Boeing Nestle Honda Toyota Ford HSBC
Lenovo
BP Sony
Revenue
US Billion
68.5 125 120 235 128 98.
9
21.
59
308
.9
86.64
Asset 64.3 126 125 370 166 2454
10.71
272.2
155.94
ProfitUS Billion
3.3 39 1.39 5.07 6.56 13.15
0.273
3.3 2.96
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TSMC (Taiwan Semicon. Manufacturing Comp.)
http://www.tsmc.com From Wiki:
Has the largest asset in Taiwan stock market, World's largest dedicated independent semiconductor foundry. Products: Apple iphone5's A6-cpu
Relation to VHDL Design idea Write VHDL TSMC chips
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Huawei Technologies Co. Ltd
http://www.huawei.com/en/ From wiki:
Telecom equipment manufacture China large private company--http://money.163.com 500 (2011-08-
25) Products: the second-largest supplier of mobile
telecommunications infrastructure equipment in theworld (after Ericsson).
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References
See course web page Digital Design Principles and Practices by John F.
Wakerly, Prentice Hall (third Edition) 2001 includesXilinx student edition).
http://www.alldatasheet.com/ www.eece.unm.edu/course/ece338/Lectures/ bas i
c -fpga -arch-xilinx.ppt High-Speed Digital Design: A Handbook of Black
Magic by Howard W. Johnson and Martin Graham,Prentice Hall, 1993. Around US$20 dollars.
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TRI-STATE LOGIC A revision: The concept of tri-state logic is essential incomputer design, so we want to revise thesetechniques before we move on.
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Appendix 1:Tri-state logic**At the float state, the wire is cut
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Input
Outputenable (OE)
Output
Input OE (input) Output0 0 Z(Float)
1 0 Z(Float)0 1 0
1 1 1
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Tri-state equivalent circuit(using output connect/cut view)
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Input
Outputenable (OE)
Output
Input
Outputenable (OE)
Output
OE=1, switch closeOE=0, switch open
Same as
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Alternatively: we can treat the Tri-state equivalentcircuit using the Rout impedance view
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Input
Outputenable (OE)
Output
Input
Outputenable (OE)
Output
OE=1, Rout= small, (e.g. 50 )OE=0, Rout=infinity (e.g. 10 M )
Same as
Rout
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Student ID: ___________,Date:_____________Name: _______________Exercise0.1:Tri-state logic with pull up resistor
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Input1
Output-Enable (OE)
Output
5V10K
Input1 Output-EnableOE (input)
Output
0 0 ? ___
1 0 ? ___
0 1 ? ___
1 1 ? ___
**At float the wire is cut
Additionalexercise:Use Rout (Impedanceview) toexplain youranswer.
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Exercise 0.2 Application 1 of Tri-state logic:
Input/Output pin OE1 controls the traffic. Fill in the cells with ?.
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Directionalcontrol(OE1)
A
B
A OutputEnableOE1 (input)
B
0 0 ?
1 0 ?
? 1 0? 1 1
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Exercise 0.3 Application 2 of Tri-state logic:
Transceivers for I/O data pins When T =1, A->B; Tcontrols the traffic,
when /OE=1, IO pins A,B are disabled
Fill in the cells with ?.
VHDL 0 (v.3A) : Introduction
A
B
/OE
T
T A OutputEnable/OE1(input)
B Whichcontrolswhich
1 0 0 ? ?
0 1 0 ? ?
? ? 1 Float ?
? Float 1 ? ?
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All data-lines are transceiver buffers A good controller will enable the CPU to read/write RAM, and read ROM
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CPU data lines
transceiversROMdatalines
RAMdatalines transceivers
transceivers/OE1, T1
/OE2, T2
/OE3,T3
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Exercise 0.4 : List OE1,2,3 and T1,2,3 forthe followings cases a) CPU writes to RAM:
/OE1=___ , /OE2___, /OE3=___, T1___, T2=____, T3_____ b) CPU reads from ROM
/OE1=___ , /OE2___, /OE3=___, T1___, T2=____, T3_____
c) CPU reads from RAM /OE1=___ , /OE2___, /OE3=___, T1___, T2=____, T3_____
V 0 (v.3 ) : t oduct o
CPU data lines
transceivers
ROMdatalines
RAMdatalines transceivers
transceivers/OE1, T1
/OE2, T2
/OE3,
T3
A
B
A B
B A
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Exercise 0.5 Application 3 of Tri-state logic:Selection of control signal (resolved logic)
Output depends on Input_A if OE is _?___ Output depends on Input_B if OE is _?___ Discuss the operation of this circuit.
VHDL 0 (v.3A) : Introduction
Input_B
Input_A Output
OE
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Exercise 0.6 Fill in ?. Discuss the operation of this circuit. Answer : nor-gate
( )
Output
OE2
5V10K
OE1
0V
0V
OE1 OE2 Output
0 0 ?
1 0 ?
0 1 ?
1 1 ?