Download - CAD: Floorplanning
Floorplanning
DoVLSI Presentation
RTL Design Flow
Physical Design –Overall Flow
Floorplanning
• Floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional blocks.
• Depending on the design methodology being followed, the actual definition of a floorplan may differ.
Why Floorplanning? The floorplanning problem is to plan the positions and shapes of the modules at the beginning of the design cycle to optimize the circuit performance:– chip area– total wirelength– delay of critical path– routability– others, e.g., noise, heat dissipation, etc.
Floorplanning
Goals• Assign shape and location of blocks.• Decide location of I/O pads.• Decide location and number of power pads.• Decide type of power distribution.• Decide location and type of clock distribution.
Objectives• Keep highly connected blocks physically close to each other.• Minimize chip area.• Minimize delay.
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Floorplanning
Input
Set of blocks.Area estimation.Possible block shapes.Number of terminals.Netlist.
Output
Shapes (Area & Aspect Ratio) and locations of blocks.
Soft Blocks• Flexible shape• I/O positions not yet determined
Hard Blocks•Fixed shape•Fixed I/O pin positions
Design Styles
Full Custom• Floorplanning is needed.
Standard Cell• Fixed cell dimensions. Floorplanning translates into a placement
problem.• Floorplanning may be required for large cells if they are
partitioned into several blocks.
Gate Array• Placement problem.
Slicing and Non-Slicing Floorplan
Slicing Floorplan: One that can be
obtained by repetitively subdividing (slicing) rectangles horizontally or vertically.
Non-Slicing Floorplan:One that may not be
obtained by repetitively subdividing alone.
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Floorplanning
Area
Deadspace
Minimizing area = Minimizing deadspace
Wire length estimation• Exact wire length not known until after
routing.
• Pin position not known.
• How to estimate?• Center to center estimation.
Floorplanning Algorithm
• Stockmeyer algorithm• Simulated annealing• Linear programming• Sequence-pair based floorplanning
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Floorplanning
• Represent floorplan by normalized polish expression.
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E = 16H7H25HV34HV
Encounter Floorplan