The VC Presentation
bob.bridge at zilkerlabs.comPhD, EE, UT, 1976CEO Zilker Labs
Agenda
Working with VCs
First Meeting Presentation example
Thanks to Eric Broockman, CEO Alereon, from whom I borrowed some of this material
Types of Pitches
The elevator pitch - interest to take the call – a hook– Remember - Ideas to VCs are like baseballs at a batting
cage; there is a new one every 10 seconds
15 minute pitch at an “Ideas/New Company” forum– 9 slides, fast paced, no deep details
• Why this team, Why this market, Why now
First meeting – 50 minutes for one or two partners – 15-30 slides – cover the whys
The Full Pitch – 2 to 3 hours: Due DiligenceThe Close - 40 minutes for full set of VC Partners– Normally a formality; Don’t blow it
The VC Business Model
VCs raise a $x00M fund, invest in ~30 companies over 2-3 years, and wait 5-7 years for the results– 1-in-10 VC investments wins VERY BIG and makes the fund
successful– 50% of VC investments fail– The other 40% have some degree of modest success, which
makes them not very interesting to the VCs
Typical VC Partner makes one, maybe two, investments per year– Partner is maxed out at about 8 board seats– Has opportunity to see 200 deals per year– Judging you with cynical eyes
The VC Presentation ProcessCEO is the single point of contactGet introduced to VCs (no cold calls)– One or two calls or emails – then move onPresent to the least important VC first– A throw-away VC– You will look stupid the first time you presentWork hard to get feedback– VCs are in the business of being polite– A friendly question can indicate a serious concern– At end, ask pointedly about their concerns
The Presentation
No NDAs with VCsStart with Team slide - very important Then you have 3-4 slides to get them truly excited!– State simply why are you going to make them a bunch of
money!– Roll out the most powerful guns you have, now!– High-level quantitative advantages are great
Then in next 20 slides describe in more detail– OK to have a wad of backup slides (with hyperlinks)
Animation can enhance, it can also distract
The Meeting
VCs get a first impression in first five minutes– Early on make your most powerful points
Learn– Listen– Listen again, ask for advice– Remember Darwin
Adapt, eye-contact, confident to the edge - Not beyond
The Meeting
Stay on message – Turn each question into an opportunity: +feedback & msg
Don’t get defensiveDon’t give handouts. “Forgot” – then find them laterBefore, During, After - ABC : Always Be Closing
Interpreting VC Feedback
“They act like they love you [which means only that they are thinking about it] until they start ignoring you” [which usually means that they have lost interest]– Friendly body language doesn’t necessarily mean that they
want to invest– They rarely tell you NO directly
Good sign – They call you after the presentation!
Bad sign– You have to call them to get further feedback or to discuss
next steps
After You Talk to a VC
The Goal: make it easy for the VCs to say yes! –remove every concern!Most VCs think the same wayRespond quickly, improve, iterate, refine, changeThe next time you present, have a rock-solid solution for every previous VC question/concernContinually strengthen your story– Be intellectually brutal with yourself
If the dog’s don’t like the formula, fix the formula
What to Expect
6-12 months of full-time work to close a first round40 VC presentations in CA, east coast and Texas8 weeks from when VCs tell they want to invest until you have money in the bankThe deal isn’t done until you see the check!
Example of ‘First Meeting’Presentation
To receive a copy of the following slides, you will need to sign an NDA with
Zilker Labs
Zilker Labs
Mission
Apply innovative mixed-signal IC technology
to solve board-level power problems
for complex electronic systems
Team
• Cygnal Integrated Products• Intermedics• Analog Devices• NASA
Ken FernaldVice President of Engineering• 16 years experience• Ph. D, EE
Work ExperiencePerson
• Cirrus• National• GE-Intersil• Siliconix
Mark AlexanderEngineering Director
• 22 years experience• BSEE
• VP and GM, Silicon Laboratories• Motorola • Analog Devices
Jim TempletonVice President of Marketing• 18 years experience• MSEE
• EIR, Austin Ventures • VP Marketing, Agere (Network Processor startup) • VP and GM, Cirrus Logic/Crystal Semiconductor• Motorola, AT&T, Bell Labs
Bob BridgeCEO• 27 years experience• Ph. D, EE
Additional Power Resources
Work ExperiencePerson
• Former CEO of Unitrode• Former CTO of Lucent’s $1B+ power business• University of California/Berkeley• University of Colorado, Boulder
Advisors• Bob Richardson• Jim Wadlington• Prof. Seth Sanders• Prof. Dragan Maksimovic
• General Partner at Sevin Rosen• Former COO of Unitrode• Former CEO of Benchmarq• 27 years of semiconductor experience
Al SchueleDirector and Chairman
The Zilker Labs AdvantageWith Zilker LabsToday
Load
Load
Load
Load
PhaseControl
VIN
Load
Load
Load
LoadDigitalDC™
DigitalDC™
DigitalDC™
DigitalDC™
VIN
DC:DCConverter
DC:DCConverter
SupplySequence
DC:DCConverter
DC:DCConverter
Mrg
Mrg
Mrg
Mrg
Mrg = margining
Monitor
Customer Benefits Realized
Benefits Realized
One supplyNon-dense PCB
Consumer
Multiple supplyHigh currentDense PCB
High Reliability
$900MMarket
PowerManagement
PowerConversion
Strategy
Mixed-signal, cost-effective, digital power-
conversion core
Patented & Innovative
system-level power
management
commodity CMOS
enables
MarketIntellectual Property
Analog Power Conversion
Customer Benefits
DigitalDigital Power ConversionPower Conversion
Simplifies PCB design
Intelligent Power ManagementIntelligent Power Management
Eliminates system-
level, power control ICs
Saves design, debug,
rework time
Design-once, use-everywhere
Improves system
availability
Four Supply Comparative Schematic
-
+ 3
21
-
+3
21
OUTPUT 1
1
0
32
CURRENT MONITOR 3
1
+
+
VREF
1
+
PG
-
+3
21
PG
VIN
1
0
+
+
LT1339
123456789
10 11121314151617181920SYNC
5VREFCTSL/ADJIAVGSSVCSGNDVFBVREF SNS+
SNS-RN/SDPHASEPGND
BG12VIN
TSTG
VBST
-
+3
21
POWER GOOD 4
1
VREF
1
-
+3
21
LT1339
123456789
10 11121314151617181920SYNC
5VREFCTSL/ADJIAVGSSVCSGNDVFBVREF SNS+
SNS-RN/SDPHASEPGND
BG12VIN
TSTG
VBST
+
POWER GOOD 3
1
PG
VREF
1
+ +
+
-
+3
21
U11
SC4201
1234
8765
RTVDDSYNCA
GNDDCB
LT1339
123456789
10 11121314151617181920
SYNC5VREFCTSL/ADJIAVGSSVCSGNDVFBVREF SNS+
SNS-RN/SDPHASEPGND
BG12VIN
TSTG
VBST
+
-
+3
21
VREF 2
1
0
+
MARG 2
1
+
VREF
1
OUTPUT 4
1
+
-
+3
21
PG
0
POWER GOOD 1
1
VREF
1
MARG 4
1
+
PG
-
+3
21
VIN RTN
1
-
+3
21
+
+
-
+ 3
21
+
-
+3
21
0
VREF 2
1
-
+3
21
+
0
+
-
+ 3
21
+
VREF
1
MARG 1
1
-
+3
21
LT1339
123456789
10 11121314151617181920
SYNC5VREFCTSL/ADJIAVGSSVCSGNDVFBVREF SNS+
SNS-RN/SDPHASEPGND
BG12VIN
TSTG
VBST
VREF 2
1
PG
-
+3
21
OUTPUT 3
1
CURRENT MONITOR 2
1
VREF
1
+
CURRENT MONITOR 4
1
VREF
1
CURRENT MONITOR 1
1
PG
OUTPUT 2
1
MARG 3
1
0
+
-
+3
21
+
-
+3
21
+
-
+3
21
-
+3
21
PG
VREF 2
1
0
VREF 2
1
POWER GOOD 2
1
• 4 output power supply with Power Good, Current Sense, Margining & Sequencing
Current Approaches
+
PG
PG
+
+
VIN RTN
1
+
+
PG
SCL
1
PG
+
PG
ZL2001
1 2 3 4 5 6 7 8
910111213141516
1718192021222324
2526272829303132
MG
NTB
DV
0V
1TS
TA
GN
DTR
IMTB
D
VSNSPVSNSMPGND
LSDSW
HSDBSTLDO
IL1
IL0
VD
DU
P1
UP
0D
LY1
DLY
0E
N
PGPH0PH1SYNCCLKOUTDGNDSCLSDA
ZL2001
1 2 3 4 5 6 7 8
910111213141516
1718192021222324
2526272829303132
MG
NTB
DV
0V
1TS
TA
GN
DTR
IMTB
D
VSNSPVSNSMPGND
LSDSW
HSDBSTLDO
IL1
IL0
VD
DU
P1
UP
0D
LY1
DLY
0E
N
PGPH0PH1SYNCCLKOUTDGNDSCLSDA
OUTPUT 1
1
ZL2001
1 2 3 4 5 6 7 8
910111213141516
1718192021222324
2526272829303132
MG
NTB
DV
0V
1TS
TA
GN
DTR
IMTB
D
VSNSPVSNSMPGND
LSDSW
HSDBSTLDO
IL1
IL0
VD
DU
P1
UP
0D
LY1
DLY
0E
N
PGPH0PH1SYNCCLKOUTDGNDSCLSDA
+
PG
OUTPUT 4
1
OUTPUT 3
1
PG
ZL2001
1 2 3 4 5 6 7 8
910111213141516
1718192021222324
2526272829303132
MG
NTB
DV
0V
1TS
TA
GN
DTR
IMTB
D
VSNSPVSNSMPGND
LSDSW
HSDBSTLDO
IL1
IL0
VD
DU
P1
UP
0D
LY1
DLY
0E
N
PGPH0PH1SYNCCLKOUTDGNDSCLSDA
VIN
1
SDA
1
OUTPUT 2
1
+
Zilker Approach
Benefits Summary
428 *1Rework time to fix sequencing and/or ramp problems
241Design Time
Design Effort
Flexibility
Material
Category
0.50.51Input voltage range
1
1
1
Zilker Labs
0.10.2Key Management Features
1.451.07BOM (including all discrete power components)
2.53Board Space
Analog PWM plus Summit
Micro IC
Analog PWM plus discrete sequencing
and monitoringRelative Metric
* Includes PCB cycle time
For 4 supplies
Intellectual Property Summary
Collapsing of system power management ICs in PoLSeamless multi-DigitalDC™ expansion– Single-phase and multi-phase load support– N+1 redundancy improves up-time– Reconfigure-able event-driven sequencing
Advanced digital conversion techniques– Digital feedback loop with feed forward control
• Stable operation over wide input voltage range– Enhanced dithering algorithms improves noise performance– Enhanced, non-linear error quantization
• Reduced ADC complexity plus good transient response
Multi-mode control pins
Reaching Customers
Large OEM Customers
ODMs
Partners:• IC vendors• FET Vendors
Module Vendors
Zilker Labs
Smaller OEM Customers
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