![Page 1: Baseband PPM and PAM Algorithm Implementation Kenneth Rice Joel Simoneau Dr. Pearson Summer Undergraduate Research Experience](https://reader035.vdocuments.mx/reader035/viewer/2022070323/56649dc75503460f94abc10d/html5/thumbnails/1.jpg)
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Baseband PPM and PAM Algorithm Implementation
Kenneth RiceJoel Simoneau
Dr. Pearson
Summer Undergraduate Research Experience
![Page 3: Baseband PPM and PAM Algorithm Implementation Kenneth Rice Joel Simoneau Dr. Pearson Summer Undergraduate Research Experience](https://reader035.vdocuments.mx/reader035/viewer/2022070323/56649dc75503460f94abc10d/html5/thumbnails/3.jpg)
Purpose
Main Objective: Create a library of available baseband
communications algorithms Secondary Objective:
Test the algorithms for efficiency and productivity based upon certain noise situations
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Outline
Pulse Amplitude Modulation Pulse Position Modulation Demodulation Techniques:
Matched Filter Time Limited Accumulation Filter
Direct/Reflect Path Noise Random Inversion Noise Algorithm Implementation Testing Future Work
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Pulse Amplitude Modulation
The amplitude of the pulses denote the information that is sent
Example:
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Pulse Position Modulation
The location of the pulse within the specified pulse frame indicates what was sent
Example
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Matched Filter
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Time Limited Accumulation
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Direct/Reflected Path Noise
When the transmitted signal changes path during transmission in such a way that the signal is inverted when received
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Random Inversion Noise
Transmitted signal randomly inverts at any given moment during transmission
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Algorithm Implementation
Pulse Amplitude Modulation (PAM) Pulse Amplitude Demodulation (PAD)
-Matched Filter Pulse Position Modulation (PPM) Pulse Position Demodulation (PPD)
-Matched Filter
-Matched Filter Altered
-Time Limited Accumulation (TLA) Filter
-TLA Altered
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FPGAs
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PAM: TRANSMITTER
Out
Digital Input
In Out
DSP
In1
In2
Out1Out2Out3
DAC 20.20313
Cont1
xladdsubz-1a+b
aba
AddSub1
Circuit: PAM
PAM: Transmitter
‘1’ -> ‘001000’
‘0’ -> ‘111000’
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PAM: RECEIVER
xlbalancez-k -1
SyncScope2
xlrelationalz-1
a
b a>b
en
Relational
xlp2sp sPtoS5
fpt dblOut2
xlmultz-3
ab (ab)
MultOut
Matched xlconvertcast
Conv1
1
Con8
0
Con5
52Con3
xladdsubz-1a-b
aba
AddSub2q
brst
Accum
Out1
Out2
Out3
ADC
Circuit: PAD
PAM: Receiver
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PAM: TRANSMITTER
ZERO
ONE xlp2sp sPtoS6
xlp2sp sPtoS10
xlmux
sel
d0
d1d1
Mux1
Out
Digital Input
In Out
DSP
In1
In2
Out1Out2Out3
DAC 2
3.277e+004
Con81024
Con14
Circuit: PPM
PPM: Transmitter
‘1’ -> 0400-Hex
‘0’ -> 8000-Hex
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PPM: MATCHED FILTER RECEIVER
In1Out1Out2Out3
Timing
xlbalancez-k -1
Sync
Scope2
xlrelationalz-1
ab a<ben
Relational2
fpt dblOut4
xlmultz-3
ab (ab)
Mult2
Out
Matched Waveform 0Con7
qbrst
Accum
Out1
Out2
Out3
ADC
Circuit: PPD-Matched
PPD: Matched Receiver
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In1Out1Out2Out3
Timing
xlbalancez-k -1
Sync
Scope2
xlrelationalz-1
ab a<ben
Relational2
fpt dblOut4
xlmultz-3
ab (ab)
Mult2
Out
Matched Waveform 0Con7
qbrst
Accum
Out1
Out2
Out3
ADC
In Out
ABS
Circuit: PPD-Matched Altered
PPD: Matched Altered Receiver
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ONE
ZERO
In1
Signal
F.Half
Reset
S.Half
Enable
Timing Controller
Scope2
xlrelational
z-1
a
b a<b
en
Relate2
fpt dbl
Out4
Out1
Out2
Out3
ADC
InOut
ABS
q
b
en
rst
2Accum
q
b
en
rst
1Accum
Circuit: PPD-TLA
PPD: TLA Receiver
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ONE
ZERO
In1
Signal
F.Half
Reset
S.Half
Enable
Timing Controller
Scope2
xlrelational
z-1
a
b a<b
en
Relate2
fpt dbl
Out4
In Out
Absolute Value1
In Out
Absolute Value
Out1
Out2
Out3
ADC
q
b
en
rst
2Accum
q
b
en
rst
1Accum
Circuit: PPD-TLA Altered
PPD: TLA Altered Receiver
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Testing
Table 1: Direct Path / Reflected Path Results
Design 101 bits 1001 bits
Matched 44 errors N/A
Matched (Altered) 0 errors 0 errors
TLA 0 errors 5 errors
TLA (Altered) 0 errors 0 errors
SNR is 4.8 for the also included Gaussian noise
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Testing (continued)
Design 101 bits 1001 bits
Matched 42 errors N/A
Matched (Altered) 24 errors 266 errors
TLA 0 errors N/A
TLA (Altered) 24 errors 266 errors
Table 2: Random Inversion Results
SNR is 4.8 for the also included Gaussian noise
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Future Work
Testing with a more accurate channel model
Quantify the relative complexity of the various algorithms to give a performance versus FPGA memory trade-off
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References
[1] L.C. Ludeman, Fudamentals of Digital Signal Processing. New York: Harper and Row, 1986.
[2] M.B. Pursley, Introduction to Digital Communications. New Jersey: Pearson Prentice Hall, 2005.