Download - Arm Lpc2292 Timing Pwm
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Pulse Width Modulation
(PWM) Waveform Generator
Reference:
LPC 2292 User Manual
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Pulse Width Modulator
Based on Timer1/Timer0 structure
Pins from 6 PWM channels: PWM1 PWM6 PWM output edges occur on timer matches
Single-edge-controlled PWM outputs (6)
All outputs go high at beginning of cycle Individual outputs go low on match
Double-edge-controlled PWM outputs (3)
Pulse edges anywhere within the period Positive or negative pulses
7 match registers control edge timing
Pulse period/width = any # of timer counts
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PWMGenerator
OutputDrivers
Shadow
Registers
Timer counter& prescaler
Match
Registers
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Single-edge PWM
Matchoutputs
PWM
OutputPins
Single-edge modulation:Match 0 sets all PWM output pins- determines period T
Match k resets PWM output pin k (k=1..6)
- determines duty cycle T1/T
T
T1
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Double-edge PWM
Matchoutputs
PWM
OutputPins
Double-edge modulation:Match 0 resets the timer, setting period TMatch 1 & 2 set/reset PWM2 (PWMSEL2=1)
- determines position & width of pulse within the periodMatch 3 & 4 set/reset PWM4, (PWMSEL4=1)
Match 5 & 6 set/reset PWM6, (PWMSEL6=1)
T
T1
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Example
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PWM registers
Identical to Timer0/Timer1 registers:
PWMTC : timer counter register PWMPC : prescale counter register
PWMPR : prescale register
PWMMR0PWMMR6: match registers
PWMIR : interrupt register
PWMTCR : timer control register
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PWM Control Register
(PWMPCR)
14 11 10 9 6 3 2 1 0
3 261 - -
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PWMSELn(n=26)
0=single-edge mode1=double-edge mode
for output PWMn
236
PWMENAn(n=16)
Enable PWMn output
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PWM Match Control Register
(PWMMCR)
20 19 18 8 7 6 5 4 3 2 1 0
Stop TC/PC when TC=PWMMR0Reset TC when TC = PWMMR0Interrupt when TC = PWMMR0
PWMMR6 . PWMMR2 PWMMR1
Action for PWMTC/PWMPC on match
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PWM Latch Enable Register
(PWMLER)6 5 4 3 2 1 0
0123456
Enable PWM match n latch (n=06)
Control update of PWM match registers during PWM generation.
Writes to PWM match register during PWM operationgo to shadow registers
On PWM match 0 event, shadow reg copied to match regif LER bit set (LER bit resets when register loaded)
Clean PWM period/duty changes at beginning of cycleExample1. Write new PWM match 1 register2. Write new PWM match 2 register3. Write to LER register with bits 1 & 2 set
4. New values to match 1 & 2 registers on next PWM match 0 event
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CPWM TImer Control Register
(PWMTCR)
11 10 9 8 7 6 5 4 3 2 1 0
Reset Enable
Timer counter &Prescale counter
PWM mode enable
Writes to match registers go toshadow registers while PWMrunning, to make changes effectiveonly at the start of a period.
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PWM Interrupt Register
(PWMIR)
10 9 8 7 6 5 4 3 2 1 0
PWMMRn: Interrupt flags for PWM match channel n (n=0..6)
Set on interrupt event, clear by writing 1 to the bit.
0123456 ----
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Example configure dual-edge PWM
void main(void) {PINSEL0 |= 0x00028000; // Enable pin 0.7 as PWM2
PWMPR = 0x00000001; // Load prescalerPWMPCR = 0x00000404; // PWM2 double-edge control, output enabled
PWMMCR = 0x00000003; // On match with timer, reset the counterPWMMR0 = 0x00000010; // Set cycle rate to 16 ticksPWMMR1 = 0x00000002; // Set rising edge of PWM2 to 2 ticksPWMMR2 = 0x00000008; // Set falling edge of PWM2 to 8 ticks
PWMLER = 0x00000007; // Enable shadow latch for match regs 0-2PWMEMR = 0x00000280; // Match 1 and Match 2 outputs set highPWMTCR = 0x00000002; // Reset counter and prescalerPWMTCR = 0x00000009; // Enable counter & PWM, release reset
while (1) { // main loop//.. // Modulate PWMMR1 and PWMMR2
}}
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Example ELEC 3050 DC Motor Speed
Controller Drive motor with PWM signal
Program one UC channel for PWM generation Motor speed reflected in output of optical
encoder Sinusoid with frequency proportional to motor speed
(500 cycles per revolution)
Square it up and count pulses per unit time to
determine motor speed
LPC 2292 Solution??