Analog CMOS Integrated Circuit Design
Introduction and Background
Dr. Jawdat Abu-Taha
Department of Electrical and Computer EngineeringIslamic University of Gaza
1
Marking
2
Assignments 10% (4 to 6)
Midterm 25%
Project 20%
Final Exam 45%
References
Recommended Textbook:
Behzad Razavi, Design of Analog CMOS IntegratedHill, 2001
Some other useful references:
Circuits, McGraw-
•
T. Chan Carusone, D. Johns and K. Martin, Analog Integrated Circuit
2ndDesign, Edition, John Wiley, 2011
P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of
5thAnalog Integrated Circuits, Edition, John Wiley, 2009
3rdD. Holberg and P. Allen, CMOS Analog Circuit Design,Oxford University Press, 2011
Edition,
3rdR. Jacob Baker, CMOS Circuit Design, Layout, and Simulation,Edition, Wiley-IEEE Press, 2010
5th 6thA. Sedra and K.C. Smith, Microelectronic Circuits,Oxford University Press, 2004, 2009
or Edition,
JournalCircuits
and conference articles including IEEE Journal of Solid-Stateand International Solid-State Circuits Conference
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Why Analog?
• Most of the physical signals are analog in nature!
• Although digital is great we need an analog interface to convertphysical signals from analog to digital
• Also, in some application after processing the signals in digital we need to convert them back to analog.
domain,
• Thus in many applications analog and mixed-signal circuits performance bottlenecks.
are the
• Also with constant process improvements the boundary of betweenhigh-speed digital and analog circuits becomes more and more fuzzy!
• That is why analog and mixed-signal designers are still and hopefully will be in demand for the foreseeable future.
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Typical Real World System
• Example:
G
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Da
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on
ve
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DSPADCFilter
AFE DSP
Intel 45 nm Process
http://blog.oregonlive.com/siliconforest/2007/11/intel11.pdf
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Background
1.
2.
3.
4.
5.
6.
7.
8.
9.
Suggested Reading
Structure of MOS Transistors
Threshold Voltage
Long-Channel Current
Regions of Operation
Transconductance
Second-Order Effects
Short-Channel Effects
MOS Layout
Equations
10.Device Capacitances
11.Small-signal Models
12.Circuit Impedance
13.Equivalent Transconductance
9SMEECE 488 – Set 1: Introduction and Background
Suggested Reading
• Most of the material in this set are based on
Chapters 2, 16, and 17 of the Razavi’sCMOS Integrated Circuits
book: Design of Analog
Many of the figures in this set are from © Design of Analog CMOS Integrated Circuits,McGraw-Hill, 2001, unless otherwise noted.
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Transistor
• Transistor stands for …
• Transistor are semiconductor devices that can be classified as
– Bipolar Junction Transistors (BJTs)
– Field Effect Transistors (FETs)
• Depletion-Mode FETs or (e.g., JFETs)
• Enhancement-Mode FETs (e.g., MOSFETs)
11
Simplistic Model
• MOS transistors have three terminals: Gate, Source, and Drain
• The voltage of the Gate terminal determinesbetween Source and Drain (Short or Open).
the type of connection
• Thus, MOS devices behave like a switch
12
NMOS PMOS
VG high Device is ON
D is shorted to S
Device is OFF
D & S are disconnected
VG low Device is OFF
D & S are disconnected
Device is ON
D is shorted to S
Physical Structure - 1
• Source and Drain terminals are identical charge carriers, and Drain receives them.
MOS devices have in fact 4 terminals:
except that Source provides
•
– Source, Drain, Gate, Substrate (bulk)
13
Physical Structure - 2
• Charge Carriers are electrons in NMOS devices,PMOS devices.
Electrons have a higher mobility than holes
and holes in
•
•
•
So, NMOS devices are faster than PMOS devices
We rather to have a p-type substrate?!
LD: Due to Side Diffusion
Poly-silicon used instead of Metalfor fabrication reasons
• Actual length of the channel (Leff) is less than the length of gate
14
Physical Structure - 3
• N-wells allow both NMOS and PMOS devices to reside on the
same piece of die.
• As mentioned, NMOS
Source, Drain, Gate,
and PMOS devices have
Substrate (bulk)
4 terminals:
• In order to have all PN junctions reverse-biased, substrate of
NMOS isof PMOS
connected to the most negative voltage, and substrateis connected to the most positive voltage.
15
Physical Structure - 4
• MOS transistor Symbols:
Source electronDrain• In NMOS Devices:
Current flows from Drain to Source
Source hole Drain• In PMOS Devices:
Current flows from Source to Drain
• Current flow determines which terminal is Source and which one
is Drain. Equivalently, source and drain can be determined basedon their relative voltages.
16
Threshold Voltage - 1
• Consider an NMOS: as the gate voltage is increased, the surfaceunder the gate is depleted. If the gate voltage increases more,free electronsformed.
appear under the gate and a conductive channel is
(a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion,
and (d) channel formation
• As mentionedchannel under
before, in NMOS devices charge carriers in thethe gate are electrons.
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Threshold Voltage - 2
• Intuitively, the threshold voltage is the gate voltage that forces theinterface (surface under the gate) to be completely depleted of charge (in
NMOS the interface is as much n-type as the substrate is p-type)
• Increasinginduces an
gate voltage above this threshold (denoted by VTH or Vt)
inversion layer (conductive channel) under the gate.
18
Threshold Voltage - 3
Analytically:
Qdep
MS 2 F VTH
Where:
Cox
MS Built - inPotential gate Silicon
the difference between the work functions of
the polysilico n gate and the silicon substrate
K T N ln sub Work Function (electrostatic potential)
F
q n i
Charge in the depletion region Qdep si F sub
19
4 q N
Threshold Voltage - 4
• In practice, the “native” threshold value may not be suited forcircuit design, e.g., VTH may be zero and the device may be on forany positive gate voltage.
• Typically threshold voltage is adjusted by ion implantation into thechannel surface (doping P-type material will increase VTH ofNMOS devices).
• When VDS is zero, there is no horizontal electric field present in the
channel, and therefore no current between the source to the drain.
• When VDS is more than zero, there is some horizontal electric field
which causes a flow of electrons from source to drain.
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Long Channel Current Equations - 1
• The voltage of the surface under the gate, V(x), depends on the voltages of Source and Drain.
• If VDS is zero, VD= VS=V(x). The charge density Qd (unit C/m) is uniform.
C WLV V
Q C V ox GS TH Q dL L L
Qd WCox (VGS VTH )
• If VDS is not zero, the channel is tapered, and V(x) is not constant. Thecharge density depends on x.
Qd (x) WCox (VGS V (x) VTH )
21
Long Channel Current Equations - 3
• Current :I
dQ dQ dx Q velocityd
dt dx dt
Velocity in terms of V(x):
dV
dtvelocity E , E
( dV (x)
) velocitydx
Qd in terms of V(x):
Qd (x) WCox (VGS V (x) VTH )
Current in terms of V(x):•© Microelectronic Circuits, 2004 Oxford University PressdV (x)
I WC [V V (x) V ]D ox GS TH ndx
VDSL
I D dx WCoxn [VGS V ( x) VTH ]dVx0 V 0
• Long-channel current equation:
W
L
1V 2
I C [(V V )V ]D n ox GS TH DS DS2
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Long Channel Current Equations - 4
• If VDS ≤ VGS-VTH we say the device is operating in triode (or linear) region.
W 1 V V V V 2• Current in Triode Region: I C D n ox GS TH DS DS
L 2
• Terminology:
W
LAspect Ratio
Overdrive Voltage Effective Voltage VGS VTH Veff
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Long Channel Current Equations - 5
• For very small VDS (deep Triode Region):
ID can be approximated to be a linear function of VDS.
The device resistance will be independent of VDS and will
only depend
The device will
on Veff.
behave like a variable resistor
2VGS VTH :
If VDS
WI D n Cox VGS VTH
VDS
L
1 VDSR ON WI
n Cox VGS VTH D
L
24
Long Channel Current Equations - 6
• Increasing VDS causes the channel to acquire a tapered shape. Eventually,
as VDS reaches VGS VTH– the channel is pinched off at the drain. Increasing
VDS above VGS – VTH has little effect (ideally, no effect) on the channel’s
shape.
© Microelectronic Circuits, 2004 Oxford University Press
• When VDS is more than VGS – VTH the channel is pinched off, and the
horizontal electric field produces a current.
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Long Channel Current Equations - 7
• If VDS VGS> – VTH, the transistor is in saturation (active) region,
and the channel is pinched off.
VGS VTHL '
I D dx WCoxn [VGS V ( x) VTH ]dVx0 V 0
1
2
W
L') 2I C (V VD n ox GS TH
• Let’s, for now, assume that L’=L. The fact that
L’ is not equal to L is a second-order effect
known as channel-length modulation.
Since ID only depends on VGS, MOS transistors in
used as current sources.
• saturation can be
26
Long Channel Current Equations - 8
• Current Equation for NMOS:
0 n
; if VGS VTH (Cut off )
WCox VGS VTH VDS ; if VGS VTH , VDS 2(VGS VTH ) (Deep Triode)
L
I D I DS
V W
L
1V V V 2
1
2
C ; if V V , V V V (Triode)n ox GS TH DS DS GS TH DS GS TH2
W
L) 2 C (V V ; if V V , V V V (Saturation )n ox GS TH GS TH DS GS TH
27
Long Channel Current Equations - 9
• Current Equation for PMOS:
0 p
; if VSG VTH (Cut off )
WCox VSG VSDVTH ; if VSG VTH , VSD 2(VSG VTH ) (Deep Triode)
L
I D I SD
W
L
1 V V 2
1
2
C V ; if V V , V V V (Triode)p ox SG TH SD SD SG TH SD SG TH
2
W
L) 2 C (V V ; if V V , V V V (Saturation )
p ox SG TH SG TH SD SG TH
28
V
Regions of Operation - 1
• Regions of Operation:
Cut-off, triode (linear), and saturation (active or pinch-off)
© Microelectronic Circuits, 2004 Oxford University Press
• Once the channel is pinched off, the current through the channel is
almost constant. As a result, the I-V curves have a very small slope in
the pinch-off (saturation) region, indicating the large channel
resistance.
29
Regions of Operation - 2
• The following illustrates the transition from pinch-off to triode region for
NMOS and PMOS devices.
• For NMOS devices:
If VD increases (VG Const.), the device will go from Triode to Pinch-off.
If VG increases (VD Const.), the device will go from Pinch-off to Triode.
** In NMOS, as VDG increases the device will go from Triode to Pinch-off.
• For PMOS devices:
If VD decreases (VG Const.), the device will go from Triode to Pinch-off.
If VG decreases (VD Const.), the device will go from Pinch-off to Triode.
** In PMOS, as VGD increases the device will go from Pinch-off to Triode.
30
Regions of Operation - 3
• NMOS Regions of Operation:
© Microelectronic Circuits, 2004 Oxford University Press
• Relative levels of the terminal voltages of the enhancement-typetransistor for different regions of operation.
NMOS
31
Regions of Operation - 4
• PMOS Regions of Operation:
© Microelectronic Circuits, 2004 Oxford University Press
• The relative levels of the terminal voltages of the enhancement-typePMOS transistor for different regions of operation.
32
Regions of Operation - 5
Example:
For the following circuit assume that VTH=0.7V.
• When is the device on?
• What is the region of operation if the device is on?
• Sketch the on-resistance of transistor M1 as a function of VG.
33
Transconductance - 1
• The drain current of the MOSFET in saturation region is ideally a
function of gate-overdrive voltage (effectivea function of VDS.
voltage). In reality, it is also
• It makes sense to define a figure of meritdevice converts the voltage to current.
that indicates how well the
• Which current are we talking about?
• What voltage is in the designer’s control?
• What is this figure of merit?
I D g m
VDS Const.VGS
34
Transconductance - 2
Example:
Plot the transconductance of the following(assume Vb is a constant voltage).
circuit as a function of VDS
• Transconductance in triode:
VGS VDSW
1
VTH VDS
2g m n Cox
VDS Const.V L 2GS
W n Cox VDS
L
Transconductance in saturation:•
1 C
W
L
) 2g (V V m n ox GS TH
VDS Const.VGS 2
W n Cox (VGS VTH )
L
Moral: Transconductance drops if the device enters the triode region.•
35
Transconductance - 3
• Transconductance, gm, in saturation:2 I D
W
W
g 2C (V V ) C I m n ox GS TH n ox DV VL L GS TH
• If the aspect ratio is constant: gm depends linearly on (VGS - VTH).
Also, gm depends on square root of ID.
• If ID is constant: gm is inversely proportional to (VGS - VTH).
Also, gm depends on square root of the aspect ratio.
• If the overdrive voltage is constant: gm depends
Also, gm depends linearly on the aspect ratio.
linearly on ID.
36
Second-Order Effects (Body Effect)
Substrate Voltage:
• So far, we assumed that the bulk and source of the transistor are at the same voltage (VB=VS).
• If VB >Vs, then the bulk-source PN junction will be forward the device will not operate properly.If VB <Vs,
biased, and
•
–
–
–
the bulk-source PN junction will be reverse biased.
the depletion region widens, and Qdep increases.
VTH will be increased (Body effect or Backgate effect).
• It can be shown that (what is the unit for :
2 q si N sub V V 2 V 2 where TH TH 0 F SB F Cox
37
Body Effect - 2
Example:
Consider the circuit below (assume the transistor is in the active region):
• If body-effect is ignored, VTH will be constant, and I1 will only depend onVGS1=Vin-Vout. Since I1 is constant, Vin-Vout remains constant.
Vin Vout VTH C Const. Vin Vout VTH C D Conts.
• In general, I1 depends on VGS1- VTH =Vin-Vout-VTH (and with body effectVTH is not constant). Since I1 is constant, Vin-Vout-VTH remains constant:
Vin Vout VTH C Const. Vin
increases, and
Vout VTH C
• As Vout increases, VSB1 as a result VTH increases.Therefore, Vin-Vout Increases.
No Body Effect With Body Effect
38
Body Effect - 3
Example:
For the following Circuit sketch the drain current of transistor M1 when VX
Assume VTH0=0.6V, =0.4V1/2, and 2F=0.7V.varies from -∞ to 0.
39
Channel Length Modulation - 1
• When a transistor is in the saturation region (VDS >
the channel is pinched off.
VGS – VTH),
L
1 W(VGS VTH )2 wherenCoxI D L' L-L• The drain current is
2
1
L
L'
1 L 1 1 1
1
L1 LL' L L LL
1L
1 1
L
1
L 1 V • Assuming we get: L V
L DS L DSL'
1
2
W
L'
1
2
WnCox VGS VTH 1 VDS
22nCoxI D (VGS VTH ) •
•
The drain current isL
As ID actually depends on both
not ideal current sources (why?).
VGS and VDS, MOS transistors are
40
Channel Length Modulation - 2
represents the relative variation in effective length of theincrement in VDS
channel for a given•
• For longer channels is smaller, i.e., L
I D • Transconductance: g mVDS Const.VGS
In Triode:W
Lg C VDSm n ox
In Saturation (ignoring channel length modulation):
2 I D
WW
g C (V V ) 2 C Im n ox GS TH n ox DL L V VGS TH
In saturation with channel length modulation:
2 I D W
W
V ) 1 V 2 C I 1 Vg C (Vm n ox GS TH DS n ox D DSL L V VGS TH
• The dependence of ID on VDS is much weaker than its dependence on VGS
41
Channel Length Modulation - 3
Example:
Given all other parameters constant, plot ID-VDS characteristic
for L=L1 and L=2L1
of an NMOS
VGS VTH VDS1VDSW
ID n Cox • In Triode Region: 2
L 2
I D W
Therefore :VDS L
1nCox
W VGS VTH 2 1 VDS
• In Saturation Region: I D
2 L
I D 1
nCoxW VGS VTH 2 So we get :
VDS 2 L
I D W W
Therefore : L2VDS L
• Changing the length of the device from L1 to 2L1 will flatten the ID-VDS
curves (slope will be divided by two in triode and by four in saturation).
• Increasing L will make a transistor a better current source, degrading its current capability.
Increasing W will improve the current capability.
while
•
42
Sub-threshold Conduction
•
•
If VGS < VTH, the drain current is not zero.
The MOS transistors behaveVBE
similar to BJTs.
VTI I e• In BJT: C S
VGS
e VTI I• In MOS:D 0
• As shown in the figure, in MOS transistors, the drain current drops byone decade for approximately each 80mV of drop in VGS.
• In BJT devices the current drops faster (one decade for approximately each 60mv of drop in VGS).
• This current is known as sub-threshold or weak-inversion conduction.
43
CMOS Processing Technology
• Top and side views of a typical CMOS process
44
CMOS Processing Technology
• Different layers comprising CMOS transistors
45
Photolithography (Lithography)
• Used to transfer circuit layout information to the wafer
46
Typical Fabrication Sequence
47
Self-Aligned Process
• Why source and drain junctions are formed after the gate oxide
and polysilicon layers are deposited?
48
Back-End Processing
• Oxide spacers and silicide
49
Back-End Processing
• Contact and metal layers fabrication
50
Back-End Processing
• Large contact areas should be avoided to minimize the
possibility of spiking
51
MOS Layout - 1
• It is beneficial to have some insight into the layout of the MOS devices.
• When laying out a design, there are many important parameters we
need to pay attention to such as: drain and source areas,
interconnects, and their connections to the silicon through contactwindows.
Design rules determine the criteria that a circuit layout must meet for a
given technology. Things like, minimum length of transistors, minimum
area of contact windows, …
•
52
MOS Layout - 2
Example:
Figures below show a circuit with a suggested layout.
• The same circuit can be laid out in different ways, producing different
electrical parameters (such as different terminal capacitances).
53
Device Capacitances - 1
•
•
The quadratic model determines the DC behavior of a MOS transistor.
The capacitances associated with the devices are important when
studying the AC behavior of a device.
There is a capacitance between any two terminals of a MOS transistor.
So there are 6 Capacitances in total.
•
• The Capacitance between Drain and Source is negligible (CDS=0).
• These capacitances will depend on the region of operation (Bias
values).
54
Device Capacitances - 2
• The following will be usedterminals:
to calculate the capacitances between
oxCox 1.
2.
Oxide Capacitance:
Depletion Capacitance:
,C1 W L Cox tox
q si N su bC C W L 2 dep
4 F
3. Overlap Capacitance: C3 C4 Cov W LD Cox C fringe
4. Junction Capacitance:
Sidewall Capacitance: C jsw Cj0
C ju n m
V1
R Bottom-plate Capacitance: C
B j
C5 C6 C j C jsw
55
Device Capacitances - 3
In Cut-off:CGS
CGD
Cov C3
Cov C4
Cchannel-bulk
1.
2.
3.
CGS: is equal to the overlap capacitance.
CGD: is equal to the overlap capacitance.
CGB: is equal to Cgate-channel = C1 in series with = C2.
4. CSB:
bulk.
CDB:
bulk.
is equal to the junction capacitance between source and
5. is equal to the junction capacitance between source and
CSB
CDB
C5
C6
56
Device Capacitances - 4
In Triode:
• The channel isolates the gate from the substrate. This means that if VG
changes, the charge of the inversion layer are supplied by the drain
and source as long as VDS is close to zero. So, C1 is divided between
gate and drain terminals, and gate and source terminals, and C2 is
divided between bulk and drain terminals, and bulk and sourceterminals.
C1
2
C1
1.
2.
3.
4.
5.
CGS:
CGD:
C CGS ov
C CGD ov2
CGB: the channel isolates the gate from the substrate. CGB 0
C2
CSB:
CDB:
C CSB 52
C2C C
DB 62
57
Device Capacitances - 5
In Saturation:
• The channel isolates the gate from the substrate. The voltage across
the channel varies which can be accounted for by adding two
and
and
equivalent capacitances to the source. One is between source
gate, and is equal to two thirds of C1. The other is between
bulk, and is equal to two thirds of C2.
source
C C 2
C1.
2.
3.
4.
5.
CGS:
CGD:
GS ov 13
CGD Cov
CGB: the channel isolates the gate from the substrate. CGB 0
CSB:
CDB:
C C 2
CSB 5 23
CDB C6
58
Device Capacitances - 6
• In summary:
ov 1ov 32
ov2
GB 1C1 C2
525 5 2
3
66
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Cut-off Triode Saturation
CGS Cov C C1 C
2C
CGD Cov C
C 1
Cov
CGBC1 C2 C C
0 0
CSBC
C C2 C
2C
CDBC
C C2
2C6
Importance of Layout
Example (Folded Structure):
Calculate the gate resistance of the circuits shown below.
Folded structure:
•
•
•
Decreases the drain capacitance
Decreases the gate resistance
Keeps the aspect ratio the same
60
Passive Devices
• Resistors
61
Passive Devices
• Capacitors:
62
Passive Devices
• Capacitors
63
Passive Devices
• Inductors
64
Latch-Up
• Due to parasitic bipolar transistors in a CMOS process
65
Small Signal Models - 1
• Small signal model is an approximation of the large-signal modelaround the operation point.
• In analog circuits most MOS transistors are biased in saturation region.
• In general, ID is a function of VGS, VDS, and VBS. We can use this Taylor
series approximation:
I D V
I D V I D VTaylorExpansion : I I second order terms
D D0 GS DS BSVGS VDS VBS
I D V I D V
I D VVDS gI g V V
D GS DS BS m GS mb BSVGS VDS VBS ro
66
Small Signal Models - 2
1 W 1 WnCox VGS VTH 1 VDS
2• Current in Saturation: 2nCoxI D (VGS VTH ) 2 L' 2 L
I D I D V
I D VI VBS• Taylor approximation: D GS DSV V VGS DS BS
• Partial Derivatives:
I D W n Cox (VGS VTH ) 1 VDS g
m
V LGS
I D 1 C
W
L
1)2 I (V V n ox GS TH D
VDS 2 ro
I D I D VTH
W
L
) 1 VDS
Cox (VGS VTH nVBS VTH VBS
2 2 F VSB
g m g m g mb
2 2 F VSB
67
Small Signal Models - 3
• Small-Signal Model:
vDSiD g m vGS g mb vBS
ro
• Terms, gmvGS and gmbvBS, can be modeled by dependent sources.
These terms have the same polarity: increasing vG, has the same
effect as increasing vB.
• The term, vDS/ro can be modeled using a resistor as shown below.
68
Small Signal Models - 4
• Complete Small-Signal Model with Capacitances:
• Small signal model including all the capacitance(qualitative) analysis of even a few-transistor circuit
makesdifficult!
the intuitive
• Typically, CAD tools are used for accurate circuit analysis
• For intuitive analysis we try to find a simplest model that canthe role of each transistor with reasonable accuracy.
represent
69
Circuit Impedance - 1
• It is often useful to determine the impedance ofspecific pair of terminals.
a circuit seen from a
• The following is the recipe to do so:
1.
2.
3.
Connect a voltage source, VX, to the port.
Suppress all independent sources.
Measure or calculate IX.
V
R X
X
IX
70
Circuit Impedance - 2
Example:
• Find the small-signal impedance of the following currentsources.
• We draw the small-signal model, which is the same for both
circuits, and connect a voltage source as shown below:
v v i g v X X
X m GS
r ro o
vX R r
X o
iX
71
Circuit Impedance - 3
Example:
•
•
Find the small-signal impedance of the following circuits.
We draw the small-signal model, which is the same for both
circuits, and connect a voltage source as shown below:
vX
vX i g v g v g v g v
X m GS mb BS m X mb X
r ro o
vX
1 1 1 R r
1
r
X o
i g g g gX m mb
m mb
o
72
Circuit Impedance - 4
Example:
• Find the small-signal impedance of the following circuit. This
circuit is known as the diode-connected load, andfrequently in analog circuits.
is used
• We drawsource as
the small-signal model andshown below:
connect the voltage
vX
vX v
1 g
i g v g v
X m GS m X X m
r r r oo o
vX
1 1R r
1
r
X o
i g gX m
m
o
• If channel length modulation is ignored (ro=∞) we get:
1 1 1R r
X o
g g gm m m
73
Circuit Impedance - 5
Example:
• Find the small-signal impedance of the followingcircuit is a diode-connected load with body effect.
circuit. This
vX
vX i g v g v g v g v
X m GS mb BS m X mb X
r ro o
v
1 g g
X m mb
r o
vX
1 1 1 1 R r r
1
r
X o
g go
i g g g gX m mb m mb
m mb
o
• If channel length modulation is ignored (ro=∞) we get:
1 1 1 1 1 R r
X o
g g g g g g g gm mb m mb m mb m mb
74
Equivalent Transconductance - 1
• Recall that the transconductance of a transistor was a a figure ofmerit that indicates how well the device converts a voltage to current.
ID g
m
V V Const.GS DS
• It is sometimes useful to define the equivalent transconductance of a
circuit as follows:I
OUTG m
V V Const.IN OUT
• The following is a small-signal block diagram of an arbitrary circuit
with a Norton equivalent at the output port. We notice that:
VOUT=Constant so vOUT=0 in the small signal model.
iOUTG
m
v 0vIN OUT
75
Equivalent Transconductance - 2
Example:
• Find the equivalent transconductance of an NMOS transistor
in saturation from its small-signal model.
i g v g vOUT m GS
iOUT
m IN
G gm m
vIN
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Equivalent Transconductance - 3
Example:
• Find the equivalent transconductance of the following circuit
when the NMOS transistor in saturation.
v v v v i RIN GS S GS OUT S
vS
i ROUT S i R i g v g v g (v i R ) g
OUT m GS mb BS m IN OUT S mb OUT S
r rO O
RS 1 g R i g R g v
OUT m S mb S m IN
r
O
i g g r G OUT m m O
r r g R g R RRS
m
v1 g R g R IN O O m S mb S S
m S mb S
rO
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Short-Channel Effects
• Threshold Reduction
– Drain-induced barrier lowering (DIBL)
• Mobility degradation
• Velocity saturation
• Hot carrier effects
– Substrate current
– Gate current
• Output impedance variation
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Threshold Voltage Variation in Short Channel Devices
• The Threshold of transistors fabricated on the same chip decreases as
the channel length decreases.
• Intuitively, the extent of depletion regions associated with drain and
source in the channel area, reduces the immobile charge that must beimaged by the charge on the gate.
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Drain-Induced Barrier Lowering (DIBL)
When the channel isvoltage increases the
short, the drainchannel surface
potential, lowering the barrier to flow
charge from source (think of increased
electric field)the threshold.
and therefore, decreasing
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Effects of Velocity Saturation
• Due to drop in mobility at high electric fields
• (a) Premature drain current saturation and (b) reduction in gm
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Hot Carrier Effects
• Short channel devices may experience high lateral drain-sourceelectric field
• Some carriers that make it to drain have high velocity (called“hot” carriers)
• “Hot” carriers may “hit” silicon atoms at high speed and causeimpact ionization
• The resulting electron and holes are absorbed by the drain andsubstrate causing extra drain-substrate current
• Really “hot” carriers may be injected into gate oxide and flow outof gate causing gate current!
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Output Impedance Variation
Recall the definition of .
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Output Impedance Variation in Short-Channel Devices
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