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Altera University ProgramCyclone V SoC Course
Blair Fort
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About the Presenter (me)
Ph.D. candidate at the University of Toronto- High-Level Synthesis as part of the LegUp group
Member of the Altera University Program since 2006- Course materials and exercises- Altera Monitor Program
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About the University Program Staff
Members:- Prof. Stephen Brown- Prof. Zvonko Vranesic- Kevin Nam- Aja Canyon- Blair Fort
Successful books in print
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Why Teach Students about FPGAs?
Field-Programmable Gate Arrays are programmable hardware chips- Can be used to implement any digital hardware circuit
Digital hardware is found is almost all modern products- Consumer produces, like audio and video players- Telephone and television equipment- Cars, airplanes, trains- Medical equipment, and industrial control
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Why Teach Students about FPGAs?
Field-Programmable Gate Arrays are programmable hardware chips- Can be used to implement any digital hardware circuit
Digital hardware is found is almost all modern products- Consumer produces, like audio and video players- Telephone and television equipment- Cars, airplanes, trains- Medical equipment, and industrial control
FPGAs are … everywhere
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About Altera Corporation
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Altera Highlights
Founded in 1983 High-growth semiconductor company Products include
- FPGAs- structured ASICs- embedded soft processors- design software- IP- development kits
3,100 employees ~$2 billion in revenue
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Altera Products
FPGAs:- Cyclone series: low cost, high performance- Arria series: Mid range, transceivers- Stratix series: largest, full featured, highest performance
Stratix 10- 2X core performance- Intel’s 14nm Tri-Gate process- 64-bit quad-core ARM Cortex-A53
CPLDs:- MAX series: for small, instant-on applications, non-volatile configuration
Design Support:- Quartus II: easy to use, complete CAD flow- Qsys System Integration tool
Development environment for embedded systems Nios II: embedded processor, ARM processor
- Embedded Design Suite: Nios II and ARM
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Altera R&D Sites
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San Jose, US• Headquarter
s
High Wycombe, UK
Toronto, Canada• New Device Architectures• CAD Algorithms• IP• University Program
Penang, Malaysia
Austin, US
Herlev, DenmarkSt. John’s, Canada
New Jersey, US
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Altera University ProgramOverview
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Altera’s University Program Advantage
Ready-to-teach course material for universities- Tutorials (written for students, not experienced engineers!)
- Lab exercises Written by experienced Professors Digital Logic, Computer Organization, Embedded Systems
- Design examples I.P. cores for all of the peripherals on our teaching boards Prebuilt Nios II and ARM computer systems for use in courses
- Software: Quartus II, Nios II and ARM development tools Easy to use, powerful tools All software licenses are free to universities
- Distributed through the Web (www.altera.com/education/univ)
Best-in-class lab boards for teaching
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DE1-SoC
$150 USD Cyclone V SoC FPGA
Dual-core ARM Cortex-A9- 1GB DDR 3 SDRAM, MicroSD
- USB, Triple-speed Ethernet
- ADC, Accelerometer
- LED, Pushbutton
FPGA- 85K Programmable Logic Elements
- 64 MB SDRAM
- DVD-quality audio in/out, Video in/VGA out
- PS/2, IrDA
- 4 debounced pushbuttons, 10 slider switches, 10 red LEDs, six 7-segment displays
- Expansion headers
Built-in USB Blaster for FPGA programming
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DE-series Design Objective
Boards are ideal for use across the curriculum:
- Introductory Digital Logic - Computer Organization- Embedded Systems- Advanced Digital Logic (System Design)- Senior Digital Design Projects
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Research Platform: DE5-Net (Stratix V)
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USB Blaster
RJ45
SFP+ x4
PCI Express x8
SW x4 LED x47-seg x2
DDR3 SO-DIMM B DDR3 SO-DIMM ASATA x4
QDR II+ SRAM
Flash
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Getting Started with the U.P.
Enroll as a member Professor at- http://university.altera.com
Receive free licenses for Quartus II CAD tools, Nios II processor, and other I.P. core designs
Request a free sample DE-series board
After evaluating the board:- Purchase additional boards (at Altera U.P. prices) from www.terasic.com or- Request a larger donation
(We also offer grants of FPGA chips for teaching & research projects)
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Altera U.P. Web Site
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Over 1,500 Universities with Altera Labs
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Canada• 50 Labs
United States• 450 Labs
Europe• 500 Labs
East Asia• 500 Labs
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ARM Cortex-A9
Tutorial #1
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ARM
Founded in November 1990
Designs the ARM range of RISC processor cores- Licenses ARM core designs to semiconductor partners who fabricate and
sell to their customers- ARM does not fabricate silicon itself
Also develop technologies to assist with the designing of the ARM architecture- Software tools, boards, debug hardware- Application software- Bus architectures- Peripherals, etc
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ARM Cortex Processor (v7) Families
ARM Cortex-A family (v7-A):- Applications processors for full OS
and 3rd party applications
ARM Cortex-R family (v7-R):- Embedded processors for real-time
signal processing, control applications
ARM Cortex-M family (v7-M):- Microcontroller-oriented processors
for MCU and SoC applications
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ARM Cortex Processor (v7) Highlights
Reduced Instruction Set Computer (RISC) architecture- aka. Load/Store architecture
16 and 32-bit instruction modes- ARM (32-bits)- Thumb (16-bits)- Thumb 2 (16/32-bits)
32-bit word-length
16 general-purpose registers
Condition code flags, usable with many types of instructions
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ARM Cortex-A9
Cyclone V SoC and Arria V SoC families- 1-2 Cores
Application-level processor
Features:- 800 MHz 32-bit processor- 32 KB instruction and data L1 caches- Snoop control unit (SCU)- Accelerator Coherency Port (ACP)- Unified 512KB L2 Cache- ARM NEON™ single instruction, multiple data (SIMD) coprocessor- Floating point unit
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ARM Cortex-A9 MPCore
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CPU 0
ARM Cortex-A9
SIMD and FPU
MMU
I-Cache D-Cache
Private Timers
Generic Interrupt Controller
CPU 1
ARM Cortex-A9
SIMD and FPU
MMU
I-Cache D-Cache
Private Timers
Accelerator Coherency Port and Snoop Controller
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ARM Cortex-A9 Registers
Arguments and Result
Register variables- Must be preserved
Scratch register
Stack Pointer Link Register Program Counter
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R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13 / SP
R14 / LR
R15 / PC
This is defined by the Procedure Call Standard for the ARM Architecture (AAPCS)
Link register stores the return address for subroutine calls
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ARM Cortex-A9 CPSR
Current Program Status Register (CPSR)
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31
N
30
Z
29
C
28
V
7
I
6
F
5
T
4 0
Condition code flags
Interrupt disable bits
ARM or Thumb operation
Processor mode
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ARM Instruction Set
32-bit instructions
Unified Assembler Language (UAL)- Common syntax for ARM and Thumb instructions
Instruction Classes- Branch instructions- Data-processing instruction- Load and store instructions- Status register access instructions- Miscellaneous instructions
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ARM Machine Code Format
Format:
Rd: Destination register
Rn: Operand 1
Operand 2- 12-bit immediate offset or- Rm (lower four bits) and shift_operand
Condition codes- For conditional execution of the instruction
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31 28 27 16 15 12 111920 0
Condition Rd Immediate or RmOP code Rn
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ARM Assembly Syntax
Operation Result, Operand 1, Operand 2
Operand 2: 12-bit immediateOP Rd, Rn, #value
Operand 2: registerOP Rd, Rn, Rm
Operand 2: register with shiftOP Rd, Rn, Rm, SHIFT #shift_value
SHIFT: left/right shift or rotate- 5-bit shift value- Changes contents of Rm prior to being used
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31 28 27 16 15 12 111920 0
Condition Rd Immediate or RmOP code Rn
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Branch Instructions
Branch target address- Program Counter (pc/r15) + 24-bit offset (2’s complement)
Syntax- B{condition code} LABEL- BEQ LOOP
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31 28 27 0
Condition Offset or Rm
24 23
OP code
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Branch Instructions
Branch target address- Program Counter (pc/r15) + 24-bit offset (2’s complement)
Syntax- B{condition code} LABEL- BEQ LOOP
Subroutine calls- Branch and Link instruction: BL LABEL- Next address is stored in LR, for return
Subroutine returns- Branch and Exchange: BX LR
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31 28 27 0
Condition Offset or Rm
24 23
OP code
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ARM Condition Codes
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Data-processing Instructions
Arithmetic- ADD, SUB, MUL, MLA (multiple accumulate)
Logic- AND, ORR, EOR- BIC (bit clear), TST (test)
Move- MOV, MVN (move negative (not)), MOVT (move top)
Shift and rotate- ASR, LSL, LSR, ROR
Comparison- CMP, CMN (compare negative)
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31 28 27 16 15 12 111920 0
Condition Rd Immediate or RmOP code Rn
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Setting Condition Codes
Always set by comparison and test instructions
Arithmetic, logic and move instruction can optionally affect the flags.- ADD R2, R3, R4 (does not affect the flags)
- ADDS R2, R3, R4 (does affect the flags)
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Conditional Execution
Most ARM instructions are executed conditionally.ADD R2, R3, R4 (always execute)ADDAL R2, R3, R4
ADDNE R2, R3, R4 (execute only if the Z flag is clear)
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Conditional Execution
Most ARM instructions are executed conditionally.ADD R2, R3, R4 (always execute)ADDAL R2, R3, R4
ADDNE R2, R3, R4 (execute only if the Z flag is clear)
Example: c = (a > b) ? (a – b) : (b – a);
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Conditional Execution
Most ARM instructions are executed conditionally.ADD R2, R3, R4 (always execute)ADDAL R2, R3, R4
ADDNE R2, R3, R4 (execute only if the Z flag is clear)
Example: c = (a > b) ? (a – b) : (b – a);
START: CMP R0, R1 BLT LESS
SUB R2, R0, R1 B ENDLESS: SUB R2, R1, R0END:
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Conditional Execution
Most ARM instructions are executed conditionally.ADD R2, R3, R4 (always execute)ADDAL R2, R3, R4
ADDNE R2, R3, R4 (execute only if the Z flag is clear)
Example: c = (a > b) ? (a – b) : (b – a);
START: CMP R0, R1 START: CMP R0, R1 BLT LESS SUBGT R2, R0, R1
SUB R2, R0, R1 SUBLE R2, R1, R0 B ENDLESS: SUB R2, R1, R0END:
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Assembler Directives
Directives provide information required by the assembler
GNU Assembler directives- .text
Identifies code section
- .global symbol Makes symbol visible outside the assembled object file
- .word expressions Comma separated expression are assembled into 32-bit numbers
- .end Marks the end of the source file
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Hands-on Session 1
Create a software project targeting the ARM Cortex-A9 Compile the application Download the compiled software to the DE1-SoC Run and debug the application
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Exercise 1: Greatest Common Divisor (GCD)
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int a = 54, b = 24;do {
if ( a > b) a = a – b;else b = b – a;
} while (a != b);
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int a = 54, b = 24;do {
if ( a > b) a = a – b;else b = b – a;
} while (a != b);
.text
.global _start
_start: MOV R0, #54 /* Register R0 is the first number. */ MOV R1, #24 /* Register R1 is the second number. */
GCD: CMP R0, R1 /* Set the condition codes. */SUBGT R0, R0, R1 /* If (R0 > R1) then R0 = R0 - R1. */SUBLT R1, R1, R0 /* If (R0 < R1) then R1 = R1 - R0. */BNE GCD /* If (R0 != R1) then loop again. */
STOP: B STOP /* If (R0 == R1) then stop. */
.end
Exercise 1: Greatest Common Divisor (GCD)
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Step 1: Start Altera Monitor Program
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Step 2: Create a New Project
Sets up the Altera Monitor Program- Select files to work with- Specify target system
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Step 2.1: Specify name, directory and architecture
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Step 2.2: Select the ARM Cortex-A9 System
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Step 2.3: Select Program Type
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Step 2.4: Add Source File
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Step 2.5: Set Board Connection and Select Processor
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Step 2.6: Leave Default Memory Settings
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Step 3: Compile and Load
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Compile your assembly language program
Load the compiled code into the memory on the DE1-SoC board
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Step 4: Disassembly Window
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Step 4: Disassembly Window
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Disassembly
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Step 4: Disassembly Window
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Registers
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Step 4: Disassembly Window
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Info & Error Msgs
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Step 4: Disassembly Window
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Terminal
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Step 4: Disassembly Window
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Step 4: Disassembly Window
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Step 5: Single Step your Program
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Step 5: Single Step your Program
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Step 6: Change Register View
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Step 7: Single Step your Program Again
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Step 8: Set a Breakpoint
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Step 9: Run to the Breakpoint
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Step 9: Run to the Breakpoint
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Step 10: Change Register View
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Step 11: Look at CPSR
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31
N
30
Z
29
C
28
V
7
I
6
F
5
T
4 0
Condition code flags
Interrupt disable bits
ARM or Thumb operation
Processor mode
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CPSR = 0x200001D3
Step 11: Look at CPSR
67
31
N
30
Z
29
C
28
V
7
I
6
F
5
T
4 0
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CPSR = 0x200001D3
Step 11: Look at CPSR
68
31
N
30
Z
29
C
28
V
7
I
6
F
5
T
4 0
0 0 1 0
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CPSR = 0x200001D3
What should have happened in our code?
Step 11: Look at CPSR
69
31
N
30
Z
29
C
28
V
7
I
6
F
5
T
4 0
0 0 1 0
GCD: CMP R0, R1SUBGT R0, R0, R1SUBLT R1, R1, R0BNE GCD
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CPSR = 0x200001D3
What should have happened in our code?
Note- GT is Z clear and N equals V- LT is N is not equal to V- NE is Z clear
Step 11: Look at CPSR
70
31
N
30
Z
29
C
28
V
7
I
6
F
5
T
4 0
0 0 1 0
GCD: CMP R0, R1SUBGT R0, R0, R1SUBLT R1, R1, R0BNE GCD
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CPSR = 0x200001D3
What should have happened in our code?
Note- GT is Z clear and N equals V- LT is N is not equal to V- NE is Z clear
Step 11: Look at CPSR
71
31
N
30
Z
29
C
28
V
7
I
6
F
5
T
4 0
0 0 1 0
GCD: CMP R0, R1SUBGT R0, R0, R1SUBLT R1, R1, R0BNE GCD
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Step 12: Set a Breakpoint at the End and Run
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Step 13: Restart the Program
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Step 14: Single Step
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Step 15: Modify R0
75
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Step 16: Run to Breakpoint
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Step 17: Disconnect from the DE1-SoC Board
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0x40 into register R1
78
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0x40 into register R1
LDR R1, [R0]
79
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0x40 into register R1
MOV R0, #0x40LDR R1, [R0]
80
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0x40 into register R1
MOV R0, #0x40LDR R1, [R0]
81
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0x40 into register R1
MOV R0, #0x40LDR R1, [R0]
82
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0x40
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0x40 into register R1
MOV R0, #0x40LDR R1, [R0]
83
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0x40
0x12345678
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
84
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
MOV R0, #0xFF200040LDR R1, [R0]
85
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
MOV R0, #0xFF200040LDR R1, [R0]
0xFF200040 is larger than 16 bits
86
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
MOV R0, #0x0040MOVT R0, #0xFF20LDR R1, [R0]
87
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
MOV R0, #0x0040MOVT R0, #0xFF20LDR R1, [R0]
88
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
MOV R0, #0x0040MOVT R0, #0xFF20LDR R1, [R0]
89
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0x40
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
MOV R0, #0x0040MOVT R0, #0xFF20LDR R1, [R0]
90
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0xFF200040
0
0x00000000
0x00000004
0x00000008
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Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
MOV R0, #0x0040MOVT R0, #0xFF20LDR R1, [R0]
91
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0xFF200040
0xFEDCBA90
0x00000000
0x00000004
0x00000008
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0x00000000
Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
LDR R0, =0xFF200040LDR R1, [R0]
92
0x00000004
0x00000008
0x00000040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
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0x00000000
Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
LDR R0, =0xFF200040LDR R1, [R0]
Assembled code:
LDR R0, [pc, #0]LDR R1, [R0]
93
0x00000004
0x00000008
0x00000040
0xFF200040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
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0x00000000
Load and Store Instructions
Reading data from memory- How do we read the memory contents at
address 0xFF200040 into register R1
LDR R0, =0xFF200040LDR R1, [R0]
Assembled code:
LDR R0, [pc, #0]LDR R1, [R0]
94
0x00000004
0x00000008
0x00000040
0xFF200040
0xFF200040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
LiteralPool
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0x00000000
Load and Store Instructions
Writing data to memory- How do we write the contents of R1 to the
memory location 0x40
LDR R0, =0x00000040STR R1, [R0]
95
0x00000004
0x00000008
0x00000040
0xFF200040
0x00000040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
![Page 96: Altera University Program Cyclone V SoC Course Blair Fort](https://reader037.vdocuments.mx/reader037/viewer/2022102516/5697c0021a28abf838cc3393/html5/thumbnails/96.jpg)
0x00000000
Load and Store Instructions
Writing data to memory- How do we write the contents of R1 to the
memory location 0x40
LDR R0, =0x00000040STR R1, [R0]
Assembled code:
LDR R0, [pc, #0]STR R1, [R0]
96
0x00000004
0x00000008
0x00000040
0xFF200040
0x00000040
…
0x12345678
…
…
0xFEDCBA90
R0
R1
0
0
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Addressing Modes
Register indirect:- Register offset: [Rn]
Offset mode:- Immediate offset: [Rn, #offset]- Register offset: [Rn, ± Rm, shift]
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Addressing Modes
Register indirect:- Register offset: [Rn]
Offset mode:- Immediate offset: [Rn, #offset]- Register offset: [Rn, ± Rm, shift]
Indexed mode:- Updates the contents of Rn
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Addressing Modes
Register indirect:- Register offset: [Rn]
Offset mode:- Immediate offset: [Rn, #offset]- Register offset: [Rn, ± Rm, shift]
Indexed mode:- Updates the contents of Rn
Pre-indexed mode:- Immediate offset: [Rn, #offset]!- Register offset: [Rn, ± Rm, shift]!
Post-indexed mode:- Immediate offset: [Rn], #offset- Register offset: [Rn], ± Rm, shift
99
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Storing and Loading Multiple Registers
Two pseudo-instructions- PUSH and POP- For storing and loading multiple registers
100
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Storing and Loading Multiple Registers
Two pseudo-instructions- PUSH and POP- For storing and loading multiple registers
- PUSH {R1, R3-R5}
- POP {R1, R3-R5}
101
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Storing and Loading Multiple Registers
Two pseudo-instructions- PUSH and POP- For storing and loading multiple registers
- PUSH {R1, R3-R5} STMDB SP!, {R1, R3-R5}
- POP {R1, R3-R5} LDMIA SP!, {R1, R3-R5}
102
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Exercise 2: Dot product
103
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Exercise 2: Dot product
104
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Exercise 2: Dot product
105
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Exercise 2: Dot product
106
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Exercise 2: Dot product
107
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Step 1: Create a New Project
Sets up the Altera Monitor Program- Select files to work with- Specify target system
108
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Step 1.1: Specify name, directory and architecture
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Step 1.2: Select the ARM Cortex-A9 System
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Step 1.3: Select Program Type
111
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Step 1.4: Add Source File
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Step 1.5: Set Board Connection and Select Processor
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Step 1.6: Leave Default Memory Settings
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Step 2: Compile and Load
115
Compile your assembly language program
Load the compiled code into the memory on the DE1-SoC board
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Step 3: Notice the use of the Literal Pool
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Step 4: Go to the Memory Window
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Step 5: Find the Address of AVECTOR
118
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Step 6: Find the Address of BVECTOR
119
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Step 7: Find the Data of the Vectors
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Step 8: Change to Signed Representation
121
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Step 8: Change to Signed Representation
122
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Step 9: Change to Decimal Format
123
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Step 9: Change to Decimal Format
124
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Step 10: Find Literal Pool in the Disassembly Window
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Step 11: Single Step or Set Breakpoints and Run
126
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Step 12: Final Result in R3
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Step 12: … And in the Memory Location DOTP
128
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Summary #1
What did we learn?- ARM Cortex-A9- Unified Assembly Language (UAL)- How to run and debug programs using the Altera Monitor Program
Where did we go from here?- Tutorials:
Introduction to the ARM Processor Altera Monitor Program Tutorial for ARM
- http://university.altera.com
- Literature: ARM Architecture Reference Manual
- http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html
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Intro to Cyclone V’sHard Processor System (HPS)
Tutorial #2
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ARM Cortex-A9 MPCore
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CPU 0
ARM Cortex-A9
SIMD and FPU
MMU
I-Cache D-Cache
Private Timers
Generic Interrupt Controller
CPU 1
ARM Cortex-A9
SIMD and FPU
MMU
I-Cache D-Cache
Private Timers
Accelerator Coherency Port and Snoop Controller
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HPS
Altera HPS Block Diagram
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MPCore
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HPS
Altera HPS Block Diagram
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MPCore
L2 Cache
0 GB
1 GB
2 GB
3 GB
4 GB
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HPS
Altera HPS Block Diagram
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MPCore
L2 Cache
0 GB
1 GB
2 GB
3 GB
4 GB
L3 Interconnect
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HPS
Altera HPS Block Diagram
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Boot ROM
MPCore
L2 Cache
Boot Region0 GB
1 GB
2 GB
3 GB
4 GB
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HPS
Altera HPS Block Diagram
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Boot ROM
MPCore
DDR3Chips
L2 Cache
SDRAMController SDRAM
Window
Boot Region0 GB
1 GB
2 GB
3 GB
4 GB
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HPS
Altera HPS Block Diagram
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Boot ROM
MPCore
DDR3Chips
L2 Cache
SDRAMController SDRAM
Window
Boot Region0 GB
1 GB
2 GB
3 GB
4 GB
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HPS
Altera HPS Block Diagram
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Boot ROM
MPCore
On-Chip RAM
DDR3Chips
L2 Cache
SDRAMController SDRAM
Window
Boot Region0 GB
1 GB
2 GB
3 GB
4 GB
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HPS
Altera HPS Block Diagram
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Boot ROM
MPCore
On-Chip RAM
Timers
DDR3Chips
L2 Cache
SDRAMController SDRAM
Window
Boot Region0 GB
1 GB
2 GB
3 GB
4 GB
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HPS
Altera HPS Block Diagram
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Boot ROM
MPCore
On-Chip RAM
GPIO
Timers
DDR3Chips
LEDGKEY
L2 Cache
SDRAMController SDRAM
Window
Boot Region0 GB
1 GB
2 GB
3 GB
4 GB
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HPS
Altera HPS Block Diagram
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController SDRAM
Window
Boot Region0 GB
1 GB
2 GB
3 GB
4 GB
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HPS
Altera HPS Block Diagram
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController SDRAM
Window
Boot Region0 GB
1 GB
2 GB
3 GB
4 GBPeripherals
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Hands-on Session 2
Write a program that uses HPS peripherals
Write a program that uses FPGA peripherals
Write a program that uses printf and scanf
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Exercise 3: HPS Peripherals
The program will use the HPS pushbutton and LED
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HPS Pushbutton and LED
Both are attached to the memory-mapped GPIO 1 port- Base address: 0xFF709000- 16 registers
Data, Interrupts, Configuration, etc.
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External Port
…
Data Register
Direction Register
Interrupt Enable
…
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HPS Pushbutton and LED
Both are attached to the memory-mapped GPIO 1 port- Base address: 0xFF709000- 16 registers
Data, Interrupts, Configuration, etc.
Each bit corresponds to a different I/O pin
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External Port
…
Data Register
Direction Register
Interrupt Enable
…
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HPS Pushbutton and LED
Both are attached to the memory-mapped GPIO 1 port- Base address: 0xFF709000- 16 registers
Data, Interrupts, Configuration, etc.
Each bit corresponds to a different I/O pin- LED
Bit 24
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External Port
…
Data Register
Direction Register
Interrupt Enable
…
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HPS Pushbutton and LED
Both are attached to the memory-mapped GPIO 1 port- Base address: 0xFF709000- 16 registers
Data, Interrupts, Configuration, etc.
Each bit corresponds to a different I/O pin- LED
Bit 24- Pushbutton
Bit 25
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External Port
…
Data Register
Direction Register
Interrupt Enable
…
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Program
Read the pushbutton and display the value on the LED
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#define bit_25_pattern 0x02000000
int main(void)(volatile int * HPS_GPIO1_Data = (int *) 0xFF709000;volatile int * HPS_GPIO1_Direction = (int *) 0xFF709004;volatile int * HPS_GPIO1_External = (int *) 0xFF709050;
*HPS_GPIO1_Direction = (1 << 24); // Set bit 24 (LEDG) of GPIO1 // to be an output
while(1){
int value = *HPS_GPIO1_External; // Read the value of the GPIO port
value &= bit_25_pattern; // Mask out the pushbutton value
*HPS_GPIO1_Data = (value >> 1); // Set the LEDG to the read value}
}
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Step 1: Create a New Project
Sets up the Altera Monitor Program- Select files to work with- Specify target system
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Step 1.1: Specify name, directory and architecture
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Step 1.2: Select the ARM Cortex-A9 System
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Step 1.3: Select Program Type
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Step 1.4: Add Source File
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Step 1.5: Set Board Connection and Select Processor
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Step 1.6: Leave Default Memory Settings
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Step 2: Compile and Load
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Compile your C language program
Load the compiled code into the memory on the DE1-SoC board
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Step 3: Go to the Memory Window
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Step 4: Jump to the GPIO’s Address Range
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Step 5: Why is the Memory Window Blank?
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Step 6: Highlight the First Two Registers of the GPIO Port
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Step 7: Right Click and Read Selected Address Range
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Step 7: Right Click and Read Selected Address Range
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Step 8: Read the GPIO’s External Port
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Step 9: Hold Down the Button and Re-read the Location
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Step 10: Disassembly Window
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Step 11: Jump to Main
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Step 11: Jump to Main
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Step 12: Set a Breakpoint and Run to Main
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Step 13: Single Step or Run
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Step 14: Stop while Holding Down the Pushbutton
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HPS
How About Communication with the FPGA?
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController SDRAM
Window
Boot Region0 GB
1 GB
2 GB
3 GB
4 GBPeripheralsFPGA
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HPS
There are Several Bridges Between the HPS and FPGA
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
FPGA
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
Bridges
SDRAMWindow
Boot Region0 GB
1 GB
2 GB
3 GB
4 GBPeripherals
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HPS
HPS-to-FPGA Bridge
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
FPGA
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
H2F
On-Chip Cores
Ports
LEDRSwitches
Etc.
SDRAMWindow
Boot Region
FPGASlave
Region
0 GB
1 GB
2 GB
3 GB
4 GBPeripherals
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FPGAHPS
Lightweight HPS-to-FPGA Bridge
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
LW H2F
Ports
LEDRSwitches
Etc.
SDRAMWindow
Boot Region
FPGASlave
Region
0 GB
1 GB
2 GB
3 GB
4 GBPeripherals
On-Chip Cores
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Exercise 4: FPGA Peripherals
Circuit must be configured in the FPGA
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Pre-built DE1-SoC Computer System
Download the system onto the DE1-SoC board- Can be configured to load on power-
up
Develop programs using the Altera Monitor Program
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Exercise 4: FPGA Peripherals
We will use the red LEDs, seven-segment display and the slider switches
In the DE1-SoC, they are connecting to the Lightweight HPS-to-FPGA bridge using the Altera Parallel I/O (PIO) component
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PIO Components
Parallel I/O (PIO) Component- Depending on the PIO’s settings, not
are registers are usable
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Edgecapture Register
…
Data Register
Direction Register
Interruptmask Register
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PIO Components
Parallel I/O (PIO) Component- Depending on the PIO’s settings, not
are registers are usable
DE1-SoC Computer- Red LEDs
Base address: 0xFF200000
- Seven segment displays Base address: 0xFF200020
- Slider switches Base address: 0xFF200040
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Edgecapture Register
…
Data Register
Direction Register
Interruptmask Register
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Program
Read switches and display on LEDs and 7-Segs
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int main(void)(volatile int * LEDs = (int *) 0xFF200000;volatile int * HEX3_HEX0 = (int *) 0xFF200020;volatile int * SW_switch = (int *) 0xFF200040;int hex_conversions[16] = {0x3F, ..., 0x71};while(1){
int value = *SW_switch;*LEDs = value;int first_digit = value & 0xF;int second_digit = (value >> 4) & 0xF;
int third_digit = (value >> 8) & 0xF;int hex_value = hex_conversions[first_digit];hex_value |= hex_conversions[second_digit] << 8;hex_value |= hex_conversions[third_digit] << 16;*HEX3_HEX0 = hex_value;
}}
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Step 1: Create a New Project
Sets up the Altera Monitor Program- Select files to work with- Specify target system
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Step 1.1: Specify name, directory and architecture
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Step 1.2: Select the DE1-SoC Computer System
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Step 1.3: Select Program Type
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Step 1.4: Add Source File
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Step 1.5: Set Board Connection and Select Processor
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Step 1.6: Leave Default Memory Settings
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Step 2: Program the FPGA with the Computer System
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Step 3: Compile and Load
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Compile your C language program
Load the compiled code into the memory on the DE1-SoC board
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Step 4: Jump to the FPGA’s Address Range
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Step 5: Read the Switches, LEDs and 7-Segs Locations
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Step 6: Toggle Some Switches and Re-read
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Step 7: Write Some Values to the LEGs and 7-Segs
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Step 8: Go to the Main Function
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Step 9: Set a Breakpoint at the Load from Switches
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Step 10: Toggle Some Switches and then Single Step
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Step 11: Single Step until the LEDs are Set
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Step 12: Single Step or Run
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HPS
Can FPGA Components access the HPS Memory?
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
FPGA
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
Bridges
On-Chip Cores
Ports
LEDRSwitches
Etc.
SDRAMWindow
Boot Region
FPGASlave
Region
0 GB
1 GB
2 GB
3 GB
4 GBPeripherals
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HPS
Yes, by using the FPGA to HPS bridge.
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
FPGA
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
F2H
On-Chip Cores
Ports
LEDRSwitches
Etc.
SDRAMWindow
FPGASlave
Region
0 GB
1 GB
2 GB
3 GB
4 GBPeripherals
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HPS
What about the MPCore’s Cached Data?
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
FPGA
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
F2H
On-Chip Cores
Ports
LEDRSwitches
Etc.
SDRAMWindow
FPGASlave
Region
0 GB
1 GB
2 GB
3 GB
4 GBPeripherals
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HPS
Accelerator Coherency Port (ACP)
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
FPGA
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
F2H
On-Chip Cores
Ports
LEDRSwitches
Etc.
SDRAMWindow
FPGASlave
Region
0 GB
1 GB
2 GB
3 GB
4 GBPeripherals
ACP ACPWindow
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HPS
What if the FPGA Requires Access to the SDRAM?
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
FPGA
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
Bridges
On-Chip Cores
Ports
LEDRSwitches
Etc.
0 GB
1 GB
2 GB
3 GB
4 GB
SDRAMWindow
FPGASlave
Region
Peripherals
ACPWindow
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HPS
FPGA to SDRAM Direct Access
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
FPGA
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
Bridges
On-Chip Cores
Ports
LEDRSwitches
Etc.
SDRAM
SDRAM
0 GB
1 GB
2 GB
3 GB
4 GB
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Exercise 5: Semihosting
Virtual Operating System
Allows C programs to make system calls- I/O functions- Time functions- File operations
Altera Monitor Program supports a subset- printf and scanf to and from the terminal window.- Some time functions
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Program
Printf, scanf and time functions
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#include <stdio.h>#include <time.h>
int main(void)(char str[64];int age = 0;// Get the initial timestampclock_t start_time = clock();while(1){
printf("What is your name?\n");scanf("%s",str);printf("What is your age?\n");scanf("%d",&age);...
}return 0;
}
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Step 1: Create a New Project
Sets up the Altera Monitor Program- Select files to work with- Specify target system
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Step 1.1: Specify name, directory and architecture
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Step 1.2: Select the DE1-SoC Computer System
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Step 1.3: Select Program Type and Sample Program
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Step 1.4: Automatically Includes Example’s Source Files
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Step 1.5: Set Board Connection and Select Processor
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Step 1.6: Leave Default Memory Settings
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Step 2: Program the FPGA with the Computer System
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Step 3: Compile and Load
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Compile your C language program
Load the compiled code into the memory on the DE1-SoC board
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Step 4: Run
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Step 5: Type in your name
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Step 6: Type in your age
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Step 7: See the Result of the Semi-hosting Functions
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Typical ARM Cortex-A9 Boot Sequence
Boot ROM- Hard coded by Altera- Determines the boot source by reading the boot select pins
Preloader- In Flash/SD Card or FPGA- Typically initializes the DDR3 SDRAM and HPS I/O pins
Boot loader- Loads and starts the operating system
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Boot Sequence with Altera Monitor Program
Resets the HPS
Halts the code in the Boot ROM
Loads a preloader into the HPS on-chip RAM- Preloader comes pre-compiled with the Monitor Program- Initializes the DDR3 SDRAM and HPS I/O pins- Enables the HPS-FPGA bridges- Disables the watchdog timers- Re-maps the DDR3 SDRAM to address 0x00000000
Loads the user’s code into the DDR3 SDRAM- Pauses the processor at the first instruction
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Summary #2
What did we learn?- Altera HPS peripherals- Memory layout of the HPS - How to communicate between the HPS and FPGA- ARM Cortex-A9 Boot Sequence
Where did we go from here?- Tutorials:
Introduction to the ARM Processor Altera Monitor Program Tutorial for ARM DE1-SoC Computer System
- http://university.altera.com
- Literature: Cyclone V Handbook
- http://www.altera.com/literature/lit-cyclone-v.jsp Address Map for HPS
- http://www.altera.com/literature/hb/cyclone-v/hps.html
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ARM’s Generic Interrupt Controller
Tutorial #3
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Processor Modes
ARM processor modes- User Non-privileged execution (user programs)- Supervisor (SVC) 1 Privileged execution (OS code)- Abort Error condition mode- Undefined Undefined instruction fetched- System “Same” as Supervisor- IRQ 2 Interrupt mode- FIQ Fast interrupt mode- Monitor Secure mode (only for “security extensions”)
1. The ARM A9 is in SVC mode after being reset2. IRQ mode is entered when a hardware interrupt occurs
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Current Program Status Register
The Current Program Status Register (CPSR) includes mode bits: writing to these bits can change the mode
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Processor mode: 10000 (User), 10001 (FIQ), 10010 (IRQ), 10011 (SVC), 10111 (Abort), 11011 (Undefined), 11111 (System)
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ARM Banked Registers for each Mode
Separate copies exist of some registers in each mode
Each mode has a unique SP and LR
SPSR is a saved copy of previous CPSR
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Modes and Exceptions
Processor mode can be changed manuallyMOV R1, #0x12 // mode bit pattern for IRQ mode
MSR CPSR, R1 // change to IRQ mode
Processor mode can be changed due to an exception
Reset of the ARM processor Error conditions
- fetched an unimplemented instruction- unaligned word read/write- unaligned instruction fetch
Execution of the SVC instruction causes an exception External hardware interrupt
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Exception Processing
main:
instructioninstruction…instructioninstruction…
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Exception
The ARM processor automatically:
1. Saves CPSR into banked SPRS2. Saves return address into banked LR3. Changes CPSR to reflect the Exception Mode4. Fetches instruction from exception vector table
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Exception Vector Table
Address Exception Priority Mode entered
0x0 Reset 1 SVC
0x4 Unimplemented instruction
6 Undefined
0x8 SVC instruction - SVC
0xC Data access violation
2 Abort
0x10 Instruction access violation
5 Abort
0x18 Interrupt 4 IRQ
0x1C Fast interrupt 3 FIQ
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Returning from an Exception
The LR is “related” to the return address:
Example: SUBS PC, LR, #4 // returns from IRQ handler
Note: SUBS with destination PC means “return from exception”. It causes SPSR to be restored back into CPSR!
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Processor mode Return address
Data Abort LR-8
IRQ, FIQ, pre-fetch Abort LR-4
SVC instruction LR
Undefined instruction LR
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Exception Vector Table (Assembly code)
.section .vectors, “ax”
B _start // reset vector
B SERVICE_UND // undefined instruction vector
B SERVICE_SVC // software interrrupt vector
B SERVICE_ABT_INST // aborted prefetch vector
B SERVICE_ABT_DATA // aborted data vector
.word 0 // unused vector
B SERVICE_IRQ // IRQ interrupt vector
B SERVICE_FIQ // FIQ interrupt vector
.text
Main: …
…
SERVICE_IRQ:
// code for handling the IRQ exception goes here
…
SUBS PC, LR, #4 // return from IRQ mode
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Exception Handlers (and Vectors) in C code
// Define the IRQ exception handlers void __attribute__ ((interrupt)) __cs3_reset (void) { … }void __attribute__ ((interrupt)) __cs3_isr_undef (void) { … }void __attribute__ ((interrupt)) __cs3_isr_swi (void) { … }void __attribute__ ((interrupt)) __cs3_isr_pabort (void) { … }void __attribute__ ((interrupt)) __cs3_isr_dabort (void) { …}void __attribute__ ((interrupt)) __cs3_isr_irq (void){
code for handling the IRQ exception goes here … }void __attribute__ ((interrupt)) __cs3_isr_fiq (void) { … }
The C compiler and linker will automatically make the exception vector table
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ARM Interrupt Architecture
GIC: handles up to 255 interrupt sources; sends IRQ to either/both A9 Cores
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Various peripherals, MMU, etc.
…
Peripheral IRQPeripheral IRQ
Peripheral IRQ
…
A9 Core A9 Core
IRQ IRQ
Generic Interrupt Controller (GIC)
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Generic Interrupt Controller (GIC)
PPI: private peripheral interrupt (IRQ for a specific processor) SPI: share peripheral interrupt (IRQ for either processor)
SGI: software generated interrupt (IRQ caused by writing to
a special register in the GIC
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Interrupt IDs
Each peripheral is assigned an interrupt ID DE1-SoC Computer Interrupt IDs:
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GIC Example
KEY interrupt signal is received by Distributor. If ID 73 is enabled for CPU 0, send to CPU Interface 0, which can send to A9 core
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Pushbutton KEYIRQ 73
(ID 73)
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Summary of Interrupt-driven Code
1. Set up vector table
2. Main program initializes SP for IRQ mode, initializes GIC for each interrupt ID, initializes peripherals (like KEY port), enables interrupts on A9 processor (CPSR bit I = 0), then loops
3. Exception handler for IRQi. Queries GIC to find the interrupt IDii. Calls the appropriate interrupt service routine (ISR)iii. Returns from exception (SUBS PC, LR, #4)
4. Interrupt Service Routine (ISR)i. Clears interrupt sourceii. Performs interrupt function
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Exercise 6: Handling Interrupts
We will look at the code required for handling interrupts generated by the FPGA’s pushbutton keys- 1. Assembly code- 2. C code
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Handling Interrupts: Assembly Code
Step 1: Set up vector table
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.section .vectors, "ax"
B _start // reset vectorB SERVICE_UND // undefined instruction vectorB SERVICE_SVC // software interrrupt vectorB SERVICE_ABT_INST // aborted prefetch vectorB SERVICE_ABT_DATA // aborted data vector.word 0 // unused vectorB SERVICE_IRQ // IRQ interrupt vectorB SERVICE_FIQ // FIQ interrupt vector
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Handling Interrupts: Assembly Code
Step 2: Set stack pointers
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/* Set up stack pointers for IRQ and SVC processor modes */MOV R1, #INT_DISABLE | IRQ_MODEMSR CPSR_c, R1 // change to IRQ modeLDR SP, =A9_ONCHIP_END - 3 // set IRQ stack to top of A9 onchip memory/* Change to SVC (supervisor) mode with interrupts disabled */MOV R1, #INT_DISABLE | SVC_MODEMSR CPSR, R1 // change to supervisor modeLDR SP, =DDR_END - 3 // set SVC stack to top of DDR3 memory
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Handling Interrupts: Assembly Code
Step 2: Enable interrupts
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/* To configure the FPGA KEYS interrupt (ID 73): * 1. set the target to cpu0 in the ICDIPTRn register (addr 0xFFFED848) * 2. enable the interrupt in the ICDISERn register (addr 0xFFFED108) */LDR R0, =0xFFFED848 // ICDIPTRn: processor targets registerLDR R1, =0x00000100 // set targets to cpu0STR R1, [R0]
LDR R0, =0xFFFED108 // ICDISERn: set enable registerLDR R1, =0x00000200 // set interrupt enableSTR R1, [R0]
...
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Handling Interrupts: Assembly Code
Step 3: Exception Handler
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SERVICE_IRQ:PUSH {R0-R7, LR}/* Read the ICCIAR from the CPU interface */LDR R4, =MPCORE_GIC_CPUIFLDR R5, [R4, #ICCIAR] // read the interrupt ID
FPGA_IRQ1_HANDLER:CMP R5, #FPGA_IRQ1
UNEXPECTED:BNE UNEXPECTED // if not recognized, stop hereBL KEY_ISR
EXIT_IRQ: /* Write to the End of Interrupt Register (ICCEOIR) */STR R5, [R4, #ICCEOIR]POP {R0-R7, LR}SUBS PC, LR, #
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Handling Interrupts: Assembly Code
Step 4: Interrupt Service Routine (ISR)
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KEY_ISR:LDR R0, =KEY_BASE // base address of pushbutton KEY parallel portLDR R1, [R0, #0xC] // read edge capture registerMOV R2, #0xFSTR R2, [R0, #0xC] // clear the interrupt
...
END_KEY_ISR:BX LR
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Step 1: Create a New Project
Sets up the Altera Monitor Program- Select files to work with- Specify target system
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Step 1.1: Specify name, directory and architecture
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Step 1.2: Select the DE1-SoC Computer System
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Step 1.3: Select Program Type
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Step 1.4: Add Source File
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Step 1.5: Set Board Connection and Select Processor
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Step 1.6: Choose the Exceptions Memory Settings
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Step 2: Program the FPGA with the Computer System
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Step 3: Compile and Load
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Compile your assembly language program
Load the compiled code into the memory on the DE1-SoC board
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Step 4: Notice the Starting Address
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Step 5: Look at the Vector Table
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Step 6: Look at the Exception Handler
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Step 7: Look at the Interrupt Service Routine
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Step 8: Set a Breakpoint at the Beginning of the ISR
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Step 9: Single Step and Notice the Change of Mode
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Step 10: Single Step and Notice the new Stack Pointer
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Step 11: Single Step and Notice the Change of Mode
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Step 12: Single Step and Notice the new Stack Pointer
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Step 13: Run the Program
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Step 14: Single Step Through the ISR
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Step 15: See the value of the Edge Capture Register
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Handling Interrupts: C Language Code
Step 1: Set up vector table
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// Define the remaining exception handlersvoid __attribute__ ((interrupt)) __cs3_reset (void){ while(1);}
void __attribute__ ((interrupt)) __cs3_isr_undef (void){ while(1);}
...
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Handling Interrupts: C Language Code
Step 2: Set stack pointers
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int stack, mode;// top of A9 onchip memory, aligned to 8 bytesstack = A9_ONCHIP_END - 7;
/* change processor to IRQ mode with interrupts disabled */mode = INT_DISABLE | IRQ_MODE;asm("msr cpsr, %[ps]" : : [ps] "r" (mode));/* set banked stack pointer */asm("mov sp, %[ps]" : : [ps] "r" (stack));
/* go back to SVC mode before executing subroutine return! */mode = INT_DISABLE | SVC_MODE;asm("msr cpsr, %[ps]" : : [ps] "r" (mode));
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Handling Interrupts: C Language Code
Step 2: Enable interrupts
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/* configure the FPGA KEYs interrupts */*((int *) 0xFFFED848) = 0x00000100;*((int *) 0xFFFED108) = 0x00000200;
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Handling Interrupts: C Language Code
Step 3: Exception Handler
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void __attribute__ ((interrupt)) __cs3_isr_irq (void){
// Read the ICCIAR from the processor interface int address = MPCORE_GIC_CPUIF + ICCIAR; int int_ID = *((int *) address);
if (int_ID == KEYS_IRQ) // check if interrupt is from the KEYs
pushbutton_ISR ();else
while (1); // if unexpected, then stay here
// Write to the End of Interrupt Register (ICCEOIR)address = MPCORE_GIC_CPUIF + ICCEOIR;*((int *) address) = int_ID;
return;}
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Handling Interrupts: C Language Code
Step 4: Interrupt Service Routine (ISR)
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void pushbutton_ISR( void ){
volatile int * KEY_ptr = (int *) KEY_BASE;volatile int * HEX3_HEX0_ptr = (int *) HEX3_HEX0_BASE;int press, HEX_bits;
press = *(KEY_ptr + 3); // read the pushbutton interrupt register*(KEY_ptr + 3) = press; // Clear the interrupt
...
return;}
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Step 1: Create a New Project
Sets up the Altera Monitor Program- Select files to work with- Specify target system
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Step 1.1: Specify name, directory and architecture
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Step 1.2: Select the DE1-SoC Computer System
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Step 1.3: Select Program Type
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Step 1.4: Add C Source File
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Step 1.5: Set Board Connection and Select Processor
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Step 1.6: Choose the Exceptions Memory Settings
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Step 2: Program the FPGA with the Computer System
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Step 3: Compile and Load
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Compile your C language program
Load the compiled code into the memory on the DE1-SoC board
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Step 4: Look at the Exception Handler
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Step 5: Set a Breakpoint at the Interrupt Service Routine
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Step 6: Set a Breakpoint and Run to the Main Function
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Step 7: Single Step through Setting the Stack Pointers
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Step 8: Run the Program
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Summary #3
What did we learn?- Banked registers- Generic Interrupt Controller- Setting the stack pointers
Where did we go from here?- Tutorials:
Introduction to the ARM Processor Altera Monitor Program Tutorial for ARM DE1-SoC Computer System
- http://university.altera.com- Literature:
Cyclone V Handbook- http://www.altera.com/literature/lit-cyclone-v.jsp
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Creating a Custom FPGA System for ARM
Tutorial #4
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HPS
What if you want to create a custom system?
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Boot ROM
Ports
MPCore
On-Chip RAM
GPIO
FPGA
Timers
DDR3Chips
LEDGKEY
USBEthernet
L2 Cache
SDRAMController
Bridges
On-Chip Cores
Ports
LEDRSwitches
Etc.
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Quartus II System Integration Tool (Qsys)
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Qsys Windows
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Selected ComponentsAnd connectivity
Messages
AvailableComponents
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Select Components to add to the System
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Configure the Components using their Wizards
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HPS Component:Adding/Removing FPGA to SDRAM Bridges
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HPS Component: Editing HPS Peripherals
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HPS Component: Editing SDRAM Parameters
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Component is now in the System
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Creating a Custom System
Select a processor- Altera HPS or a Nios II
Add off-the-shelf with standard interfaces (SPI, I2C, JTAG, etc.) to help solve the problem- Use existing drivers or write one yourself- Sometimes an existing driver needs to be augmented for a particular
application
Add custom components when the needed ones are not available (or too expensive)
Add I/O as needed Write code to run on the system
- Usually a single program
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How to put them together?
Qsys system integration tool- Add components
Quartus II software- Synthesize circuit for the FPGA
Altera Monitor Program- For compiling and debugging software
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Hands-on Session 4
Build a system using the Qsys system integration tool
Compile the system using the Quartus II software
Download the system to the board
Run the previous software application
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Exercise 7: Making a Custom System
Using Qsys make a system with:
- Altera HPS component
- PIO cores for: Red LEDs Seven Segments Displays Slider switches
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Step 1: Open the DE1_SoC Project in Quartus II
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Step 2: Open the DE1_SoC Project in Quartus II
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Step 3: Launch Qsys
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Step 4: Select the Computer System
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Step 5: The Pre-Started System
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Step 6: Add PIO Component for the LEDRs
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Step 7: Configure the PIO for the LEDRs
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Step 8: Add and Configure a PIO for the 7-Segs
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Step 9: Add and Configure a PIO for the Switches
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Step 10: Current System
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Step 11: Export PIOs’ External Connections
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Step 12: Minimize the PIOs
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Step 13: Make Connections
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Step 14: Go to Address Map Tab
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Step 15: Set the Slave Addresses
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Step 16: Generate the System
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Step 17: Generate the System
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Step 18: System Generation Finished
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Step 18: Generated System
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FPGA
LEDs
7-Segs
Switches
HPSHPS
module Computer_System (clk_clk,reset_reset_n,
// LEDsledr_export,
// Seven Segshex3_hex0_export,
// Slider Switchessw_export,
...);
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Step 19: Create Top Level File for project
System must be instantiated in your design- Must connect system ports to the I/O ports
In this demo the top level file has been created for you- Compile your project.
Approximately 2 minutes.- Open the DE1_SoC.v to examine the system connectivity while Quartus II
compiles the project.
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Step 20: Compile the System in Quartus II
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Step 21: Wait for Compilation to Finish
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Step 22: Create a New Project
Sets up the Altera Monitor Program- Select files to work with- Specify target system
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Step 22.1: Specify name, directory and architecture
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Step 22.2: Select a Custom System
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Step 22.3: Select Program Type
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Step 22.4: Add Source File
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Step 22.5: Set Board Connection and Select Processor
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Step 22.6: Leave Default Memory Settings
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Step 23: Program the FPGA with the Custom System
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Step 24: Compile and Load
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Compile your C language program
Load the compiled code into the memory on the DE1-SoC board
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Step 25: View Memory Content
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Step 26: Run the Program
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Summary #4
What did we learn?- How to create a custom system with the Altera HPS component
Where did we go from here?- Tutorials:
Introduction to the Altera Qsys System Integration Tool Making Qsys Components Quartus II Introduction
- http://university.altera.com
- Literature: Quartus II Handbook
- Volume 1: Section II. System Design with Qsys- http://www.altera.com/literature/lit-qts.jsp
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Other Tools
Tutorial #5
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ARM DS-5 Altera Edition
ARM Development Studio 5 (DS-5)- Eclipse Based IDE- Baremetal & Linux Development and Debug
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What Makes DS-5 FPGA Adaptive?
Altera USB-Blaster Support- A single cable to debug FPGA & SOC simultaneously
QSys CMSIS Generation and Peripheral Discovery- DS-5 automatically adapts to the peripherals on the FPGA
Cross-triggering between the CPU and FPGA domains- Want to know why that Soft IP keeps sending unexpected interrupts?
Add customer performance counters in FPGA fabric to DS-5 Streamline
CoreSight compatible FPGA IP is visible from DS-5- Make your very own non-intrusive debug-able IP core
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StreamlineSystem-Level Performance Analysis
Performance analysis of Linux systems- Profiling reports from process-level
down to assembly level- Support for software events and
CPU performance counters- Requires only a TCP connection
to the target
Streamline enables- Analyse how your software runs
on single & multi-core targets- Spot bottlenecks and code
inefficiencies- Can also analyse power usage with a third party adapter
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Keil
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Keil
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Summary #5
What did we learn?- About other available tools for ARM
Where did we go from here?- Tutorials:
Introduction to the ARM Processor Using ARM Toolchain- http://university.altera.com
- Literature: Altera SoC Embedded Design Suite User Guide
- http://www.altera.com/literature/lit-soc.jsp
- Software: ARM DS-5 License Request
- http://www.arm.com/support/university/educators/processor/microprocessor-systemsapplications-software-tools-for-educators.php
Keil- http://www.keil.com/
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Thank You
http://university.altera.com/