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VITU N I V E R S I T Y
ECE 301 - VLSI System Design(Fall 2011)
Verilog HDL -
Prof.S.Sivanantham
VIT UniversityVellore, Tamilnadu. India
E-mail: [email protected]
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After completing this lecture, you will be able to:
Understand the features of loop constructs
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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A while loop
executes until the condition is false.shall not be executed at all if the condition_expr starts out.
while ( condition_expr ) statement;
while (count < 12) count
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module zero_count_while (data, out);input [7:0] data;output reg [3:0] out; //output declared as register integer i;always @(data) begin
out = 0; i = 0;
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// an example illustrating how to count the trailing zeros in a byte.module trailing_zero_while (data, out);input [7:0] data;output reg [3:0] out; // output declared as register
always @(data) begin
out = 0; i = 0;while (data[i] == 0 && i
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module zero_count_for (data, out);input [7:0] data;output reg [3:0] out; // output declared as register integer i;always @(data) begin
out = 0;=
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// an example illustrating how to count the trailing zeros in a byte.module trailing_zero_for (data, out);input [7:0] data;
integer i; // loop counter always @(data) begin
out = 0;for (i = 0; data[i] == 0 && i
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A repeat loop performs a loop a fixed number of times.
repeat ( counter_expr ) statement;
coun er_expr can e a cons an , a var a e or a s gnavalue.counter ex r is evaluated onl once before startin the _ execution of statement (loop).
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Examples:i = 0;repeat ( 32) begin
state[i] = 0; // initialize to zerosi = i + 1; // next item
end
repeat ( cycles ) begin // cycles must be evaluated to a number = .
i
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A forever loop continuously performs a loop until the $finishtas s encountere . t
is equivalent to a while loop with an always true.
can be exited by the use of disable statement.
forever statement;
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The forever statement exampleinitial begin
clock